Author Name: Christian Fibich
Original Redmine Issue: 967 from https://www.veripool.org

When I try to P&R a VQM netlist exported by Verilog::Perl in Quartus,
I get the following error message for (approximately) every @defparam@ statement

P&R of the original netlist works fine.

Setup:

• Verilog::Perl from git (@f569a8c vrename quote tests@)
• Quartus II 13.0
• Synplify Pro

Minimal example (see attached script):

1. Synthesize HDL design with Synplify for Altera, using VQM as netlist format
2. Load generated netlist in Verilog::Perl
3. Export netlist out of Verilog::Perl via using @$nl->verilog_text()@
4. (Try to) compile exported VQM netlist in Quartus

An obvious fix would concern the @verilog_text@ method in Netlist/Module.pm.
There, we would need to output the matching Verilog::Netlist::Defparam statements
in the loop through all instantiated cells.