Author Name: Amol Nagapurkar
Original Redmine Issue: 981 from https://www.veripool.org
Original Date: 2015-10-21
Original Assignee: Wilson Snyder (@wsnyder)

Following is my code.
Module 'a' is base module, which has "my_data" as a two dimensional signal.

Module top, which has 2 instance of module 'a'. I like to instantiate the module a with Different parameter values for NUM & TUM.

At the top level expected declaration should be as below.
input [TEST0_NUM-1:0] TEST0_my_data [TEST0_TUM];
input [TEST1_NUM-1:0] TEST1_my_data [TEST1_TUM];

but after completing auto, the "NUM" parameter is translated correctly as TEST0_NUM & TEST1_NUM, but not TUM.
The verilog-auto-inst-param-value is set as "true"

Thanks in advance.

module a(
parameter NUM=1;
parameter TUM=80;
input [NUM-1:0] my_data[TUM];
);

endmodule

module top (/AUTOARG/
// Inputs
TEST1_my_data, TEST0_my_data
)
/AUTOINPUT/
// Beginning of automatic inputs (from unused autoinst inputs)
input [TEST0_NUM-1:0] TEST0_my_data [TUM]; // To a_0 of a.v
input [TEST1_NUM-1:0] TEST1_my_data [TUM]; // To a_1 of a.v
// End of automatics
/AUTOOUTPUT/
/AUTOWIRE/

/*
a AUTO_TEMPLATE
(
.(.) (TEST@_\1[][]),
);
/
a #(/AUTOINSTPARAM/
// Parameters
.NUM (TEST0_NUM), // Templated
.TUM (TEST0_TUM)) // Templated
a_0 (/AUTOINST/
// Inputs
.my_data (TEST0_my_data/[TEST0_NUM-1:0]/)); // Templated

a #(/AUTOINSTPARAM/
// Parameters
.NUM (TEST1_NUM), // Templated
.TUM (TEST1_TUM)) // Templated
a_1 (/AUTOINST/
// Inputs
.my_data (TEST1_my_data/[TEST1_NUM-1:0]/)); //Templated

endmodule
// Local Variables:
// verilog-auto-inst-param-value:true
// End: