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module auto_mda;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [0] [1:0] mda; // From a0 of a.v, ...
wire [1:0] sda; // From a0 of a.v, ...
// End of automatics
/* a AUTO_TEMPLATE (
.sda (sda[@]),
.mda (mda[@][]),
); */
a a0
(/*AUTOINST*/
// Outputs
.sda (sda[0]), // Templated
.mda (mda[0][1:0])); // Templated
a a1
(/*AUTOINST*/
// Outputs
.sda (sda[1]), // Templated
.mda (mda[1][1:0])); // Templated
b b
(/*AUTOINST*/
// Inputs
.sda (sda[1:0]),
.mda (mda/*[1:0][1:0]*/));
endmodule
module a (output sda,
output [1:0] mda)
endmodule
module b (input [1:0] sda,
input [1:0][1:0] mda);
endmodule
For some reason Verilog-mode correctly declares "sda", but generates invalid syntax for "mda". In the past, I've worked around by hand declaring the signals. But it seems like verilog-mode should be able to figure out the correct declaration (which it does correctly for typedef'ed signals).
The text was updated successfully, but these errors were encountered:
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-10-31T00:44:54Z
Brad, the first problem is the syntax is ambiguous, should it make a packed or unpacked array? The second and probably bigger problem is the packing function to combine vectors is already fairly complicated, so this won't be something quick to improve.
Author Name: Brad Dobbie
Original Redmine Issue: 986 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
For some reason Verilog-mode correctly declares "sda", but generates invalid syntax for "mda". In the past, I've worked around by hand declaring the signals. But it seems like verilog-mode should be able to figure out the correct declaration (which it does correctly for typedef'ed signals).
The text was updated successfully, but these errors were encountered: