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Misalignment of labeled assertions inside if...else... #988

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veripoolbot opened this issue Oct 30, 2015 · 1 comment
Open

Misalignment of labeled assertions inside if...else... #988

veripoolbot opened this issue Oct 30, 2015 · 1 comment
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Author Name: Bernd Beuster
Original Redmine Issue: 988 from https://www.veripool.org

verilog-version 2015-09-21-d3012e9-vpo
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-11-19T13:28:46Z

Still a problem, perhaps someone would like to contribute a patch?

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