You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Hi.
Assume you have 2 instances of the same module, and you need a big AUTO_TEMPLATE for them.
Most of the signals in the 2 instances need the same AUTO_TEMPLATE, only few signals need to be different .
Is there a way to tell the Verilog-mode to modify only the few signals for the second instance, and keep the rest of the signals as specified by first AUTO_TEMPLATE ?
Regards,
yorams70
The text was updated successfully, but these errors were encountered:
Author Name: Yoram Stern
Original Redmine Message: 1750 from https://www.veripool.org
Hi.
Assume you have 2 instances of the same module, and you need a big AUTO_TEMPLATE for them.
Most of the signals in the 2 instances need the same AUTO_TEMPLATE, only few signals need to be different .
Is there a way to tell the Verilog-mode to modify only the few signals for the second instance, and keep the rest of the signals as specified by first AUTO_TEMPLATE ?
Regards,
yorams70
The text was updated successfully, but these errors were encountered: