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Question: AUTO_TEMPLATE inheritance #989

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veripoolbot opened this issue Nov 10, 2015 · 3 comments
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Question: AUTO_TEMPLATE inheritance #989

veripoolbot opened this issue Nov 10, 2015 · 3 comments
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@veripoolbot
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Author Name: Yoram Stern
Original Redmine Message: 1750 from https://www.veripool.org


Hi.
Assume you have 2 instances of the same module, and you need a big AUTO_TEMPLATE for them.
Most of the signals in the 2 instances need the same AUTO_TEMPLATE, only few signals need to be different .

Is there a way to tell the Verilog-mode to modify only the few signals for the second instance, and keep the rest of the signals as specified by first AUTO_TEMPLATE ?

Regards,
yorams70

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-11-11T01:05:16Z


Sorry, not cleanly, but you can use the e.g. lisp AUTO_TEMPLATE syntax to select a different connection.

Also you can of course wire up the instances symmetrically then just use a "wire" assignment outside the module to do appropriate renames.

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-11-11T01:06:54Z


Presumably you know this also, but for a few exceptions they are usually put above the AUTOINST.

    fifo_s data_fifo (
                      // Inputs
                      .clk                  (fifo_clk),
                      /*AUTOINST*/);

@veripoolbot
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Original Redmine Comment
Author Name: Yoram Stern
Original Date: 2015-11-11T11:09:10Z


Thanks,
You are correct- I know that- just forgot...

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