// DESCRIPTION: Verilator: Verilog Test module
//
// This test examines Verilator against paramter definition with functions.
// Particularly the function takes in argument which is multi-dimentional.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Johan Bjork

module mod #(
     parameter real HZ = 0
);
//verilator no_inline_module
  initial begin
     $display("%f", HZ);
  end
endmodule

module t();
mod #(.HZ(123.45)) mod1();
mod #(.HZ(24.45)) mod2();

initial begin
    $write("*-* All Finished *-*\n");
    $finish;
end
endmodule

	cd obj_dir/t_param_real &&  make -f/home/phb/hs/src/vats.verilator/ext/public/verilator/git/build/verilator/test_regress/Makefile_obj VM_PREFIX=Vt_param_real CPPFLAGS_DRIVER=-DT_PARAM_REAL    Vt_param_real    > obj_dir/t_param_real/vlt_gcc.log
make: *** No rule to make target `Vt_param_real_mod__H24.cpp', needed by `Vt_param_real__ALLboth.cpp'.  Stop.