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Author Name: Johan Bjork
Original Redmine Issue: 998 from https://www.veripool.org
Original Date: 2015-11-12
Original Assignee: Wilson Snyder (@wsnyder)
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
interface intf
#(parameter PARAM = 0)
();
logic val;
endinterface
module t1(intf mod_intf);
initial begin
$display("%d", mod_intf.val);
end
endmodule
module t();
generate
if(1) begin // : Test
intf #(.PARAM(1)) my_intf;
t1 t (.mod_intf(my_intf));
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endgenerate
endmodule
results in
%Error: Internal Error: t/t_gen_named.v:20: ../V3LinkDot.cpp:1120: No symbol for interface cell: my_intf
The text was updated successfully, but these errors were encountered:
Original Redmine Comment
Author Name: Johan Bjork
Original Date: 2015-11-12T05:21:02Z
So what happens here is that the Interface cell gets renamed to it's dotted name , but the IfaceRefDType cellname keeps the old, non-dotted name. Later on when V3LinkDot tries to find the cell it uses the wrong name and fails.
I'm guessing something needs to happen in LinkDotFindVisitor perhaps. Any ideas?
Original Redmine Comment
Author Name: Johan Bjork
Original Date: 2015-11-13T17:25:03Z
Wilson,
Would you mind taking a quick look here and see if you have some ideas how this might best be fixed? I'm quite lost in what happens in the interaction of FindLinkDot and V3LinkDot and how this is supposed to work. Happy to do the patch but if you have some ideas it'd be greatly appreciated.
Author Name: Johan Bjork
Original Redmine Issue: 998 from https://www.veripool.org
Original Date: 2015-11-12
Original Assignee: Wilson Snyder (@wsnyder)
Testcase pushed to https://github.com/phb/verilator-dev/tree/gen_intf_symboltable.
results in
%Error: Internal Error: t/t_gen_named.v:20: ../V3LinkDot.cpp:1120: No symbol for interface cell: my_intf
The text was updated successfully, but these errors were encountered: