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Issues

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# Project Status Priority Subject Assignee Updated
1376 Verilator Resolved Normal Incorrect array contents in FST and LXT2 output formats Wilson Snyder 12/19/2018 01:53 AM
1377 Verilator AskedReporter Normal Segmentation Fault when tracing is enabled Wilson Snyder 12/16/2018 12:26 AM
1372 Verilator Resolved Normal XML output insufficiently qualified Wilson Snyder 12/13/2018 03:19 AM
1355 Verilator AskedReporter Normal Multi-thread example: --threads 1 (compile error) Wilson Snyder 10/05/2018 12:54 AM
1313 Verilog-mode Confirmed Normal AUTOINST problem for module containing clocking block Wilson Snyder 06/01/2018 12:24 PM
892 Verilog-mode Feature Normal Auto-assignment via pattern matching Wilson Snyder 11/19/2017 01:58 PM
585 Verilog-mode Confirmed Normal Problem with verilog-pretty-declarations function and parameter/localparam keywords, fix in attachment Wilson Snyder 11/19/2017 01:15 PM
665 SVN::S4 Feature Normal speedup s4 update after viewspec change Wilson Snyder 11/19/2017 01:02 PM
418 SVN::S4 Confirmed Normal aliased entries in s4_state cause warnings on s4 update Wilson Snyder 11/19/2017 01:02 PM
417 SVN::S4 Feature Normal Potential new s4 commands: doview and unview Wilson Snyder 11/19/2017 01:02 PM
419 SVN::S4 Confirmed Normal s4 update fails to remove a view when it is removed from viewspec Wilson Snyder 11/19/2017 01:02 PM
416 SVN::S4 Feature Normal s4 view command support for regexps at multiple levels of directory hierarchy Wilson Snyder 11/19/2017 01:01 PM
986 Verilog-mode Feature Normal AUTOWIRE misdeclares multidimensional arrays Wilson Snyder 10/31/2015 12:44 AM
526 Verilog-Perl Feature Normal Support UVM Wilson Snyder 06/21/2012 01:10 PM
449 Verilator Confirmed Normal Using public accessor tasks/functions to read and write registers causes BLKANDNBLK error Wilson Snyder 03/07/2012 02:09 PM
1378 Verilator Resolved Low SystemVerilog array initialization crashes verilator with no useful error message Wilson Snyder 12/19/2018 01:42 AM
385 Verilator Feature Low Dpi exported tasks with array inputs don't compile. Wilson Snyder 07/15/2012 03:19 PM
364 Verilator Feature Low blocking & non-blocking assigns -- verilator issues error when no logical conflict exists Wilson Snyder 04/15/2012 08:28 PM
    (1-18/18)

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