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# Project Status Priority Subject Assignee Updated
1369 Verilator Confirmed Normal Raise error / warning on continous assignment to reg Wilson Snyder 12/07/2019 05:44 PM
1526 Verilog-mode Resolved Normal SystemVerilog cast on input ports causes signal to be ignored Wilson Snyder 09/27/2019 12:26 PM
1313 Verilog-mode Confirmed Normal AUTOINST problem for module containing clocking block Wilson Snyder 07/15/2019 07:07 PM
1447 Verilog-mode Feature Normal Expand AUTOINST default values for parameters Wilson Snyder 05/29/2019 10:46 PM
1430 Verilator AskedReporter Normal Broken node on indexed interface modport Wilson Snyder 05/22/2019 02:06 AM
892 Verilog-mode Feature Normal Auto-assignment via pattern matching Wilson Snyder 11/19/2017 01:58 PM
585 Verilog-mode Confirmed Normal Problem with verilog-pretty-declarations function and parameter/localparam keywords, fix in attachment Wilson Snyder 11/19/2017 01:15 PM
665 SVN::S4 Feature Normal speedup s4 update after viewspec change Wilson Snyder 11/19/2017 01:02 PM
418 SVN::S4 Confirmed Normal aliased entries in s4_state cause warnings on s4 update Wilson Snyder 11/19/2017 01:02 PM
417 SVN::S4 Feature Normal Potential new s4 commands: doview and unview Wilson Snyder 11/19/2017 01:02 PM
419 SVN::S4 Confirmed Normal s4 update fails to remove a view when it is removed from viewspec Wilson Snyder 11/19/2017 01:02 PM
416 SVN::S4 Feature Normal s4 view command support for regexps at multiple levels of directory hierarchy Wilson Snyder 11/19/2017 01:01 PM
986 Verilog-mode Feature Normal AUTOWIRE misdeclares multidimensional arrays Wilson Snyder 10/31/2015 12:44 AM
526 Verilog-Perl Feature Normal Support UVM Wilson Snyder 06/21/2012 01:10 PM

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