• Sign in
• Register

Search:

Issues

• View all issues

Issues

If you wish to add a new issue, you must log in and create an account; "New Issue" will then appear in the menu bar. Sorry, but this was necessary to prevent form-filling spam.

---

Filters

Add filter   Status Project Tracker Priority Author Assignee Target version Category Subject Description Estimated time % Done IssueAssignee's roleCreated Updated ClosedRelated to Duplicates Duplicated by Blocks Blocked by Precedes Follows Copied to Copied from Parent task Subtasks

Options

Columns	Available Columns Tracker Parent task Author Category Target version Estimated time Total estimated time % Done Created Closed Related issues Selected Columns Project Status Priority Subject Assignee Updated
Group results by	Project Tracker Status Priority Author Assignee Category Target version % Done
Show	Description
Totals	Estimated time

Apply Clear

	#	Project	Status	Priority	Subject	Assignee	Updated
	1425	Verilator	WillNotFix	Normal	Sensitivity lists with boolean expressions		05/01/2019 10:32 PM
	1388	Verilator	Closed	Normal	Circular typedef causes infinite loop	Wilson Snyder	01/28/2019 12:32 PM
	1387	Verilator	Closed	Normal	Internal error when task is used to assign subscripted vector	Wilson Snyder	01/28/2019 12:32 PM
	1386	Verilator	Closed	Normal	Reading free memory after unrolling a gen loop	Wilson Snyder	01/28/2019 12:32 PM
	1385	Verilator	Closed	Normal	Uninitialized data written to dependency file, if executable is found from PATH	Wilson Snyder	01/28/2019 12:32 PM
	1384	Verilator	Closed	Normal	File-extension language option not consistently applied	Wilson Snyder	03/24/2019 01:15 AM
	1383	Verilator	Closed	Normal	Support SystemVerilog void casts & warn if not present	Wilson Snyder	03/24/2019 01:15 AM
	1382	Verilator	AskedReporter	Normal	Inconsistent LITENDIAN warnings on arrays		12/22/2019 08:10 PM
	1381	Verilator	Closed	Normal	"Duplicate declaration of cell" diagnostic with missing location	Wilson Snyder	01/28/2019 12:32 PM
	1366	Verilator	AskedReporter	Normal	Large increase in design header file with threads and tracing		11/29/2018 11:13 PM
	1365	Verilator	Duplicate	Normal	False BLKANDNBLK error for different signals in a vector		11/07/2018 06:42 PM
	1353	Verilator	NoFixNeeded	Normal	Convergence failures, how to debug		10/05/2018 11:53 AM

(1-12/12)

Also available in: Atom CSV