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	#	Project	Status	Priority	Subject	Assignee	Updated
	212	Verilator	Closed	Normal	Using the CXX environment variable to choose a compiler	Wilson Snyder	01/22/2010 12:35 PM
	199	Verilator	Closed	Normal	Two signals can't have the same enum	Wilson Snyder	01/07/2010 12:08 AM
	213	Verilator	Closed	Normal	The order of packed dimensions is backwards	Wilson Snyder	01/26/2010 01:08 PM
	175	Verilator	Closed	Normal	Support the increment operator in for loops	Byron Bradley	02/07/2010 12:41 PM
	172	Verilator	Closed	Normal	Support signal declarations in loop initialisers	Byron Bradley	02/07/2010 12:38 PM
	206	Verilator	Closed	Normal	Support multi-dimensional packed arrays of wires	Wilson Snyder	01/25/2010 12:52 PM
	171	Verilator	Closed	Normal	Support multi-dimensional arrays as inputs/outputs	Byron Bradley	02/07/2010 12:37 PM
	201	Verilator	Closed	Normal	Support implicit signals in both branches of a generate(if..else)	Wilson Snyder	02/07/2010 12:41 PM
	170	Verilator	Closed	Normal	Support assignment of slices of multidimensional arrays	Byron Bradley	02/07/2010 12:37 PM
	207	Verilator	Closed	Normal	Support assignment between packed arrays with different dimensions	Byron Bradley	04/02/2014 03:22 AM
	208	Verilator	Closed	Normal	Signals in a concatenation on the LHS aren't created implicitly	Byron Bradley	01/20/2010 12:35 AM
	205	Verilator	Closed	Normal	Signal declarations in for loops don't work everywhere	Byron Bradley	02/07/2010 12:42 PM
	265	Verilator	Closed	Normal	Problem with clocks after commit e57d0047184	Wilson Snyder	12/08/2010 01:42 AM
	179	Verilator	Closed	Normal	Make parentheses around a single module parameter optional	Byron Bradley	02/07/2010 12:41 PM
	224	Verilator	WillNotFix	Normal	Level sensitive always blocks are executed even when nothing has changed		03/17/2010 02:25 PM
	176	Verilator	Closed	Normal	Internal error with packed arrays	Wilson Snyder	11/05/2009 02:59 PM
	210	Verilator	Closed	Normal	Internal error caused by signals declared and initialized together inside a block	Wilson Snyder	02/07/2010 12:42 PM
	226	Verilator	Closed	Normal	Improve error handling on slices of packed arrays	Byron Bradley	05/01/2010 07:02 PM
	196	Verilator	Closed	Normal	Implicit Vars aren't always created under Pins	Wilson Snyder	02/07/2010 12:41 PM
	215	Verilator	Closed	Normal	Fix conditional assignments of slices where conditional is an array	Byron Bradley	02/01/2010 11:53 AM
	178	Verilator	Closed	Normal	Division >64-bits fails on a 32-bit build	Wilson Snyder	02/07/2010 12:41 PM
	197	Verilator	Closed	Normal	Compile errors in verilatedimp.h with STLPort 5.1.3 and RHEL4	Wilson Snyder	12/11/2009 12:00 PM
	247	Verilator	Closed	Normal	commit ed17581f92c introduces new UNOPTFLAT warnings	Wilson Snyder	04/19/2010 05:59 PM
	227	Verilator	Closed	Normal	Bitwise reductions on signals with >1 packed dimension generates incorrect code	Byron Bradley	08/09/2012 02:06 AM

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