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# Project Status Priority Subject Assignee Updated
180 Verilog-mode Closed Normal Struct pack signed misindents Michael McNamara 12/10/2009 11:48 AM
218 Verilog-mode Closed Normal pure virtual indentation Michael McNamara 06/03/2010 12:40 AM
1487 Verilator Closed Normal New WIDTH warnings on genvars Todd Strader 08/29/2019 11:15 PM
1618 Verilator Closed Normal Travis Mail not going to authors? Todd Strader 12/07/2019 04:35 PM
99 Verilator Closed Normal Internal error on case statement with identical cases. Wilson Snyder 06/23/2009 11:05 PM
173 Verilator Closed Normal Support enums Wilson Snyder 02/07/2010 12:40 PM
174 Verilator Closed Normal Add support for typedef Wilson Snyder 02/07/2010 12:41 PM
181 Verilator Closed Normal Support struct and union Wilson Snyder 07/31/2012 10:53 PM
376 Verilator Closed Normal Support "parameter type" Wilson Snyder 05/19/2016 01:17 AM
1174 Verilator Closed Normal Shift gives VL_SHIFTR_IIW not declared Wilson Snyder 06/22/2017 10:37 PM
1248 Verilator Closed Normal Large structures expose GCC/clang compile time bug Wilson Snyder 01/02/2018 11:14 PM
1607 Verilator Closed Normal CI: Add gtkwave include diff to extended tests Wilson Snyder 11/19/2019 03:11 AM
124 Verilog-Perl Closed Normal Spurious parse errors with a file with many blank lines Wilson Snyder 02/04/2005 04:34 PM
125 Verilog-Perl Closed Normal Failure to correctly parse buses of concatenated bits Wilson Snyder 01/09/2007 11:36 AM
129 Verilog-Perl Closed Normal wire declaration is wrong when add new net Wilson Snyder 01/25/2007 03:27 PM
153 Verilog-Perl Closed Normal Verilog Perl does not parse widths correctly Wilson Snyder 12/09/2010 11:09 PM
154 Verilog-Perl Closed Normal Error making Verilog-Perl-3.011 Wilson Snyder 02/08/2009 09:10 AM
155 Verilog-Perl Closed Normal Verilog packages Error Wilson Snyder 04/07/2009 06:36 AM
157 Verilog-Perl Closed Normal typo in VParseLex.l Wilson Snyder 12/04/2007 11:30 AM
158 Verilog-Perl Closed Normal macro with systemVerilog lexical delimiter fails if white spaces present in macro calling Wilson Snyder 03/27/2008 10:38 AM
159 Verilog-Perl Closed Normal Bug in Verilog-Perl: rand Wilson Snyder 03/31/2008 05:41 PM
160 Verilog-Perl Closed Normal Bug in Verilog-Perl - MIN:TYP:MAX delays in assign Wilson Snyder 03/31/2008 05:05 PM
161 Verilog-Perl Closed Normal Output Register init value Wilson Snyder 04/14/2008 05:14 PM
162 Verilog-Perl Closed Normal nested macros are not expanded correctly if a macro has arguments ... Wilson Snyder 02/08/2009 09:14 AM
164 Verilog-Perl Closed Normal Test 04critic written badly Wilson Snyder 09/29/2008 01:48 PM
(26-50/73) Per page: 25, 100

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