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# Project Status Priority Subject Assignee Updated
1540 Verilator Feature Normal Improve internal elaboration algorithm 10/06/2019 01:00 PM
1539 Verilator Feature Normal Improve internals of inliner 10/06/2019 12:54 PM
1542 Verilator Feature Normal Improve performance of bit operations by vectorizing 10/06/2019 01:24 PM
1543 Verilator Feature Normal Improve performance of icache 10/06/2019 01:23 PM
99 Verilator Closed Normal Internal error on case statement with identical cases. Wilson Snyder 06/23/2009 11:05 PM
1657 Verilator New Normal Investigate google build? Todd Strader 12/21/2019 03:36 PM
1248 Verilator Closed Normal Large structures expose GCC/clang compile time bug Wilson Snyder 01/02/2018 11:14 PM
114 IPC::Locker NoFixNeeded Normal Locking issues Wilson Snyder 09/19/2009 07:47 AM
119 Verilog-Perl NotEnoughInfo Normal MacOSX 10.4 installation Wilson Snyder 04/14/2008 05:15 PM
158 Verilog-Perl Closed Normal macro with systemVerilog lexical delimiter fails if white spaces present in macro calling Wilson Snyder 03/27/2008 10:38 AM
162 Verilog-Perl Closed Normal nested macros are not expanded correctly if a macro has arguments ... Wilson Snyder 02/08/2009 09:14 AM
1487 Verilator Closed Normal New WIDTH warnings on genvars Todd Strader 08/29/2019 11:15 PM
1628 Verilator Confirmed Normal Ongoing cleanup of SymbiFlow sv-tests (help wanted) 12/15/2019 10:41 PM
1629 Verilator WillNotFix Normal Optimize wide vectors to use 64 bit entries Wilson Snyder 12/09/2019 02:55 AM
161 Verilog-Perl Closed Normal Output Register init value Wilson Snyder 04/14/2008 05:14 PM
113 IPC::Locker Closed Normal pidwatch issue on cygwin-thread-multi-64int Wilson Snyder 02/08/2009 09:09 AM
218 Verilog-mode Closed Normal pure virtual indentation Michael McNamara 06/03/2010 12:40 AM
838 Verilog-mode Confirmed Normal randsequence misindented 11/19/2017 01:17 PM
255 SystemPerl Closed Normal rt57469: Parallel build fails Wilson Snyder 05/24/2010 02:04 PM
582 Verilog-Perl Closed Normal rt81501: Test failures due to hash randomisation in perl 5.17.6 Wilson Snyder 11/28/2012 01:47 PM
1174 Verilator Closed Normal Shift gives VL_SHIFTR_IIW not declared Wilson Snyder 06/22/2017 10:37 PM
124 Verilog-Perl Closed Normal Spurious parse errors with a file with many blank lines Wilson Snyder 02/04/2005 04:34 PM
180 Verilog-mode Closed Normal Struct pack signed misindents Michael McNamara 12/10/2009 11:48 AM
376 Verilator Closed Normal Support "parameter type" Wilson Snyder 05/19/2016 01:17 AM
377 Verilator Feature Normal Support classes and methods 02/06/2016 11:16 PM
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