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# Project Status Priority Subject Assignee Updated
582 Verilog-Perl Closed Normal rt81501: Test failures due to hash randomisation in perl 5.17.6 Wilson Snyder 11/28/2012 01:47 PM
181 Verilator Closed Normal Support struct and union Wilson Snyder 07/31/2012 10:53 PM
459 Verilog-Perl Closed Normal Comment starting line number wrong Wilson Snyder 05/04/2012 09:51 PM
379 Verilator Feature Normal Support dynamic memory new and delete 03/02/2012 11:42 PM
378 Verilator Feature Normal Support properties and assertions 03/02/2012 11:42 PM
382 Verilog-mode Closed Normal Support UVM Wilson Snyder 09/07/2011 04:34 PM
296 Verilog-mode Closed Normal Use derived-mode prog-mode? 12/14/2010 09:36 PM
153 Verilog-Perl Closed Normal Verilog Perl does not parse widths correctly Wilson Snyder 12/09/2010 11:09 PM
282 Verilog-Perl Closed Normal Escaped identifiers that are keywords are unescaped Wilson Snyder 09/20/2010 07:32 PM
270 Verilog-mode Closed Normal AUTOINST and SystemVerilog interfaces Wilson Snyder 08/18/2010 02:19 PM
218 Verilog-mode Closed Normal pure virtual indentation Michael McNamara 06/03/2010 12:40 AM
255 SystemPerl Closed Normal rt57469: Parallel build fails Wilson Snyder 05/24/2010 02:04 PM
95 Verilog-mode Closed Normal Attributes indent incorrectly Michael McNamara 03/31/2010 05:28 PM
222 Verilog-Perl Closed Normal An example in Verilog::EditFiles doesn't work Wilson Snyder 03/29/2010 06:54 PM
174 Verilator Closed Normal Add support for typedef Wilson Snyder 02/07/2010 12:41 PM
173 Verilator Closed Normal Support enums Wilson Snyder 02/07/2010 12:40 PM
200 Verilog-Perl Closed Normal Support modports in interfaces Wilson Snyder 01/21/2010 09:23 PM
180 Verilog-mode Closed Normal Struct pack signed misindents Michael McNamara 12/10/2009 11:48 AM
191 Verilog-Perl Closed Normal Define with formal matching $pli call gets misexpanded Wilson Snyder 11/24/2009 02:58 PM
106 Verilog-Perl Closed Normal Fix escaped identifiers in preprocessor 09/30/2009 04:03 PM
114 IPC::Locker NoFixNeeded Normal Locking issues Wilson Snyder 09/19/2009 07:47 AM
99 Verilator Closed Normal Internal error on case statement with identical cases. Wilson Snyder 06/23/2009 11:05 PM
121 Verilog-Perl NotEnoughInfo Normal Error building Verilog-Perl 3.121 Wilson Snyder 06/01/2009 09:45 PM
155 Verilog-Perl Closed Normal Verilog packages Error Wilson Snyder 04/07/2009 06:36 AM
109 Vregs Closed Normal Autogenerated code produces incorrect C/C++ syntax Wilson Snyder 02/25/2009 04:29 PM
(26-50/73) Per page: 25, 100

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