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# Project Status Priority Subject Assignee Updated
1567 Verilator Feature Normal Cocotb Integration 12/22/2019 08:02 PM
1606 Verilator Resolved Normal Complete string methods (starter project) 12/15/2019 01:14 PM
1607 Verilator Closed Normal CI: Add gtkwave include diff to extended tests Wilson Snyder 11/19/2019 03:11 AM
1618 Verilator Closed Normal Travis Mail not going to authors? Todd Strader 12/07/2019 04:35 PM
1628 Verilator Confirmed Normal Ongoing cleanup of SymbiFlow sv-tests (help wanted) 12/15/2019 10:41 PM
1629 Verilator WillNotFix Normal Optimize wide vectors to use 64 bit entries Wilson Snyder 12/09/2019 02:55 AM
1650 Verilator Feature Normal Implement type_reference (medium starter task) 12/20/2019 01:23 AM
1657 Verilator New Normal Investigate google build? Todd Strader 12/21/2019 03:36 PM
1537 Verilator Feature Low Support FST structure tracing w/GTKwave 10/06/2019 12:31 PM
1544 Verilator Closed Low Improve readme Wilson Snyder 11/08/2019 03:34 AM
1580 Verilator Closed Low test_regress/t_prot_lib is unstable Todd Strader 11/05/2019 01:51 PM
1637 Verilator Feature Low Support $displayb/o/h, $writeb/o/h (starter project) 12/15/2019 01:38 AM
1638 Verilator Feature Low Support $ferror/$fflush (starter task) 12/15/2019 01:40 AM
1639 Verilator Feature Low Support $countbits (starter task) 12/15/2019 01:42 AM
95 Verilog-mode Closed Normal Attributes indent incorrectly Michael McNamara 03/31/2010 05:28 PM
180 Verilog-mode Closed Normal Struct pack signed misindents Michael McNamara 12/10/2009 11:48 AM
218 Verilog-mode Closed Normal pure virtual indentation Michael McNamara 06/03/2010 12:40 AM
270 Verilog-mode Closed Normal AUTOINST and SystemVerilog interfaces Wilson Snyder 08/18/2010 02:19 PM
296 Verilog-mode Closed Normal Use derived-mode prog-mode? 12/14/2010 09:36 PM
382 Verilog-mode Closed Normal Support UVM Wilson Snyder 09/07/2011 04:34 PM
838 Verilog-mode Confirmed Normal randsequence misindented 11/19/2017 01:17 PM
955 Verilog-mode Confirmed Normal End mis-indents with sized replication 03/26/2018 08:48 PM
106 Verilog-Perl Closed Normal Fix escaped identifiers in preprocessor 09/30/2009 04:03 PM
119 Verilog-Perl NotEnoughInfo Normal MacOSX 10.4 installation Wilson Snyder 04/14/2008 05:15 PM
120 Verilog-Perl NoFixNeeded Normal syntax error, unexpected "do", expecting "IDENTIFIER" Wilson Snyder 07/31/2008 07:49 AM
(26-50/73) Per page: 25, 100

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