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# Project Status Priority Subject Assignee Updated
604 Verilator Closed Normal -x-initial-edge breaks with logic bug fix Jeremy Bennett 01/17/2013 12:21 PM
1487 Verilator Closed Normal New WIDTH warnings on genvars Todd Strader 08/29/2019 11:15 PM
1580 Verilator Closed Low test_regress/t_prot_lib is unstable Todd Strader 11/05/2019 01:51 PM
1618 Verilator Closed Normal Travis Mail not going to authors? Todd Strader 12/07/2019 04:35 PM
99 Verilator Closed Normal Internal error on case statement with identical cases. Wilson Snyder 06/23/2009 11:05 PM
173 Verilator Closed Normal Support enums Wilson Snyder 02/07/2010 12:40 PM
174 Verilator Closed Normal Add support for typedef Wilson Snyder 02/07/2010 12:41 PM
181 Verilator Closed Normal Support struct and union Wilson Snyder 07/31/2012 10:53 PM
376 Verilator Closed Normal Support "parameter type" Wilson Snyder 05/19/2016 01:17 AM
1174 Verilator Closed Normal Shift gives VL_SHIFTR_IIW not declared Wilson Snyder 06/22/2017 10:37 PM
1248 Verilator Closed Normal Large structures expose GCC/clang compile time bug Wilson Snyder 01/02/2018 11:14 PM
1544 Verilator Closed Low Improve readme Wilson Snyder 11/08/2019 03:34 AM
1607 Verilator Closed Normal CI: Add gtkwave include diff to extended tests Wilson Snyder 11/19/2019 03:11 AM
1629 Verilator WillNotFix Normal Optimize wide vectors to use 64 bit entries Wilson Snyder 12/09/2019 02:55 AM
838 Verilog-mode Confirmed Normal randsequence misindented 11/19/2017 01:17 PM
955 Verilog-mode Confirmed Normal End mis-indents with sized replication 03/26/2018 08:48 PM
296 Verilog-mode Closed Normal Use derived-mode prog-mode? 12/14/2010 09:36 PM
95 Verilog-mode Closed Normal Attributes indent incorrectly Michael McNamara 03/31/2010 05:28 PM
180 Verilog-mode Closed Normal Struct pack signed misindents Michael McNamara 12/10/2009 11:48 AM
218 Verilog-mode Closed Normal pure virtual indentation Michael McNamara 06/03/2010 12:40 AM
270 Verilog-mode Closed Normal AUTOINST and SystemVerilog interfaces Wilson Snyder 08/18/2010 02:19 PM
382 Verilog-mode Closed Normal Support UVM Wilson Snyder 09/07/2011 04:34 PM
106 Verilog-Perl Closed Normal Fix escaped identifiers in preprocessor 09/30/2009 04:03 PM
123 Verilog-Perl Closed Normal directories return in resolve_filename instead of filenames 01/27/2005 11:23 AM
1200 Verilog-Perl Closed Normal Concat parsing issue 09/09/2017 01:56 AM
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