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# Project Status Priority Subject Assignee Updated
376 Verilator Closed Normal Support "parameter type" Wilson Snyder 05/19/2016 01:17 AM
1639 Verilator Feature Low Support $countbits (starter task) 12/15/2019 01:42 AM
1637 Verilator Feature Low Support $displayb/o/h, $writeb/o/h (starter project) 12/15/2019 01:38 AM
1638 Verilator Feature Low Support $ferror/$fflush (starter task) 12/15/2019 01:40 AM
377 Verilator Feature Normal Support classes and methods 02/06/2016 11:16 PM
379 Verilator Feature Normal Support dynamic memory new and delete 03/02/2012 11:42 PM
173 Verilator Closed Normal Support enums Wilson Snyder 02/07/2010 12:40 PM
1537 Verilator Feature Low Support FST structure tracing w/GTKwave 10/06/2019 12:31 PM
1538 Verilator Feature Normal Support full UVM parsing and XML dump 10/06/2019 01:26 PM
378 Verilator Feature Normal Support properties and assertions 03/02/2012 11:42 PM
181 Verilator Closed Normal Support struct and union Wilson Snyder 07/31/2012 10:53 PM
1541 Verilator Feature Normal Support unpacked structs 10/06/2019 01:24 PM
1580 Verilator Closed Low test_regress/t_prot_lib is unstable Todd Strader 11/05/2019 01:51 PM
1618 Verilator Closed Normal Travis Mail not going to authors? Todd Strader 12/07/2019 04:35 PM
95 Verilog-mode Closed Normal Attributes indent incorrectly Michael McNamara 03/31/2010 05:28 PM
270 Verilog-mode Closed Normal AUTOINST and SystemVerilog interfaces Wilson Snyder 08/18/2010 02:19 PM
955 Verilog-mode Confirmed Normal End mis-indents with sized replication 03/26/2018 08:48 PM
218 Verilog-mode Closed Normal pure virtual indentation Michael McNamara 06/03/2010 12:40 AM
838 Verilog-mode Confirmed Normal randsequence misindented 11/19/2017 01:17 PM
180 Verilog-mode Closed Normal Struct pack signed misindents Michael McNamara 12/10/2009 11:48 AM
382 Verilog-mode Closed Normal Support UVM Wilson Snyder 09/07/2011 04:34 PM
296 Verilog-mode Closed Normal Use derived-mode prog-mode? 12/14/2010 09:36 PM
222 Verilog-Perl Closed Normal An example in Verilog::EditFiles doesn't work Wilson Snyder 03/29/2010 06:54 PM
160 Verilog-Perl Closed Normal Bug in Verilog-Perl - MIN:TYP:MAX delays in assign Wilson Snyder 03/31/2008 05:05 PM
159 Verilog-Perl Closed Normal Bug in Verilog-Perl: rand Wilson Snyder 03/31/2008 05:41 PM
(26-50/73) Per page: 25, 100

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