General

Profile

[logo] 
 
Home
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  IPC::Locker
  Parallel::Forker
  Voneline
General Info
  Papers

Issues

If you wish to add a new issue, you must log in and create an account; "New Issue" will then appear in the menu bar. Sorry, but this was necessary to prevent form-filling spam.
Filters

Apply Clear

# Project Status Priority Subject Assignee Updated
582 Verilog-Perl Closed Normal rt81501: Test failures due to hash randomisation in perl 5.17.6 Wilson Snyder 11/28/2012 01:47 PM
296 Verilog-mode Closed Normal Use derived-mode prog-mode? 12/14/2010 09:36 PM
838 Verilog-mode Confirmed Normal randsequence misindented 11/19/2017 01:17 PM
955 Verilog-mode Confirmed Normal End mis-indents with sized replication 03/26/2018 08:48 PM
95 Verilog-mode Closed Normal Attributes indent incorrectly Michael McNamara 03/31/2010 05:28 PM
180 Verilog-mode Closed Normal Struct pack signed misindents Michael McNamara 12/10/2009 11:48 AM
218 Verilog-mode Closed Normal pure virtual indentation Michael McNamara 06/03/2010 12:40 AM
270 Verilog-mode Closed Normal AUTOINST and SystemVerilog interfaces Wilson Snyder 08/18/2010 02:19 PM
382 Verilog-mode Closed Normal Support UVM Wilson Snyder 09/07/2011 04:34 PM
377 Verilator Feature Normal Support classes and methods 02/06/2016 11:16 PM
378 Verilator Feature Normal Support properties and assertions 03/02/2012 11:42 PM
379 Verilator Feature Normal Support dynamic memory new and delete 03/02/2012 11:42 PM
621 Verilator Closed Normal Enable duplicate gate elimination in ~3.848. 06/02/2013 06:54 PM
1538 Verilator Feature Normal Support full UVM parsing and XML dump 10/06/2019 01:26 PM
1539 Verilator Feature Normal Improve internals of inliner 10/06/2019 12:54 PM
1540 Verilator Feature Normal Improve internal elaboration algorithm 10/06/2019 01:00 PM
1541 Verilator Feature Normal Support unpacked structs 10/06/2019 01:24 PM
1542 Verilator Feature Normal Improve performance of bit operations by vectorizing 10/06/2019 01:24 PM
1543 Verilator Feature Normal Improve performance of icache 10/06/2019 01:23 PM
1566 Verilator Confirmed Normal FST dumping is slow 10/17/2019 10:39 PM
1567 Verilator Feature Normal Cocotb Integration 12/22/2019 08:02 PM
1606 Verilator Resolved Normal Complete string methods (starter project) 12/15/2019 01:14 PM
1628 Verilator Confirmed Normal Ongoing cleanup of SymbiFlow sv-tests (help wanted) 12/15/2019 10:41 PM
1650 Verilator Feature Normal Implement type_reference (medium starter task) 12/20/2019 01:23 AM
604 Verilator Closed Normal -x-initial-edge breaks with logic bug fix Jeremy Bennett 01/17/2013 12:21 PM
(26-50/73) Per page: 25, 100

Also available in: Atom CSV