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# Project Status Priority Subject Assignee Updated
129 Verilog-Perl Closed Normal wire declaration is wrong when add new net Wilson Snyder 01/25/2007 03:27 PM
95 Verilog-mode Closed Normal Attributes indent incorrectly Michael McNamara 03/31/2010 05:28 PM
270 Verilog-mode Closed Normal AUTOINST and SystemVerilog interfaces Wilson Snyder 08/18/2010 02:19 PM
955 Verilog-mode Confirmed Normal End mis-indents with sized replication 03/26/2018 08:48 PM
218 Verilog-mode Closed Normal pure virtual indentation Michael McNamara 06/03/2010 12:40 AM
838 Verilog-mode Confirmed Normal randsequence misindented 11/19/2017 01:17 PM
180 Verilog-mode Closed Normal Struct pack signed misindents Michael McNamara 12/10/2009 11:48 AM
382 Verilog-mode Closed Normal Support UVM Wilson Snyder 09/07/2011 04:34 PM
296 Verilog-mode Closed Normal Use derived-mode prog-mode? 12/14/2010 09:36 PM
604 Verilator Closed Normal -x-initial-edge breaks with logic bug fix Jeremy Bennett 01/17/2013 12:21 PM
174 Verilator Closed Normal Add support for typedef Wilson Snyder 02/07/2010 12:41 PM
1607 Verilator Closed Normal CI: Add gtkwave include diff to extended tests Wilson Snyder 11/19/2019 03:11 AM
1567 Verilator Feature Normal Cocotb Integration 12/22/2019 08:02 PM
1606 Verilator Resolved Normal Complete string methods (starter project) 12/15/2019 01:14 PM
621 Verilator Closed Normal Enable duplicate gate elimination in ~3.848. 06/02/2013 06:54 PM
1566 Verilator Confirmed Normal FST dumping is slow 10/17/2019 10:39 PM
1650 Verilator Feature Normal Implement type_reference (medium starter task) 12/20/2019 01:23 AM
1540 Verilator Feature Normal Improve internal elaboration algorithm 10/06/2019 01:00 PM
1539 Verilator Feature Normal Improve internals of inliner 10/06/2019 12:54 PM
1542 Verilator Feature Normal Improve performance of bit operations by vectorizing 10/06/2019 01:24 PM
1543 Verilator Feature Normal Improve performance of icache 10/06/2019 01:23 PM
1544 Verilator Closed Low Improve readme Wilson Snyder 11/08/2019 03:34 AM
99 Verilator Closed Normal Internal error on case statement with identical cases. Wilson Snyder 06/23/2009 11:05 PM
1657 Verilator New Normal Investigate google build? Todd Strader 12/21/2019 03:36 PM
1248 Verilator Closed Normal Large structures expose GCC/clang compile time bug Wilson Snyder 01/02/2018 11:14 PM
(26-50/73) Per page: 25, 100

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