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# Project Status Priority Subject Assignee Updated
109 Vregs Closed Normal Autogenerated code produces incorrect C/C++ syntax Wilson Snyder 02/25/2009 04:29 PM
270 Verilog-mode Closed Normal AUTOINST and SystemVerilog interfaces Wilson Snyder 08/18/2010 02:19 PM
160 Verilog-Perl Closed Normal Bug in Verilog-Perl - MIN:TYP:MAX delays in assign Wilson Snyder 03/31/2008 05:05 PM
159 Verilog-Perl Closed Normal Bug in Verilog-Perl: rand Wilson Snyder 03/31/2008 05:41 PM
1607 Verilator Closed Normal CI: Add gtkwave include diff to extended tests Wilson Snyder 11/19/2019 03:11 AM
459 Verilog-Perl Closed Normal Comment starting line number wrong Wilson Snyder 05/04/2012 09:51 PM
1200 Verilog-Perl Closed Normal Concat parsing issue 09/09/2017 01:56 AM
191 Verilog-Perl Closed Normal Define with formal matching $pli call gets misexpanded Wilson Snyder 11/24/2009 02:58 PM
123 Verilog-Perl Closed Normal directories return in resolve_filename instead of filenames 01/27/2005 11:23 AM
621 Verilator Closed Normal Enable duplicate gate elimination in ~3.848. 06/02/2013 06:54 PM
154 Verilog-Perl Closed Normal Error making Verilog-Perl-3.011 Wilson Snyder 02/08/2009 09:10 AM
282 Verilog-Perl Closed Normal Escaped identifiers that are keywords are unescaped Wilson Snyder 09/20/2010 07:32 PM
1 TestProject Closed Normal Example issue 04/16/2008 11:13 PM
125 Verilog-Perl Closed Normal Failure to correctly parse buses of concatenated bits Wilson Snyder 01/09/2007 11:36 AM
106 Verilog-Perl Closed Normal Fix escaped identifiers in preprocessor 09/30/2009 04:03 PM
99 Verilator Closed Normal Internal error on case statement with identical cases. Wilson Snyder 06/23/2009 11:05 PM
1248 Verilator Closed Normal Large structures expose GCC/clang compile time bug Wilson Snyder 01/02/2018 11:14 PM
158 Verilog-Perl Closed Normal macro with systemVerilog lexical delimiter fails if white spaces present in macro calling Wilson Snyder 03/27/2008 10:38 AM
162 Verilog-Perl Closed Normal nested macros are not expanded correctly if a macro has arguments ... Wilson Snyder 02/08/2009 09:14 AM
1487 Verilator Closed Normal New WIDTH warnings on genvars Todd Strader 08/29/2019 11:15 PM
161 Verilog-Perl Closed Normal Output Register init value Wilson Snyder 04/14/2008 05:14 PM
113 IPC::Locker Closed Normal pidwatch issue on cygwin-thread-multi-64int Wilson Snyder 02/08/2009 09:09 AM
218 Verilog-mode Closed Normal pure virtual indentation Michael McNamara 06/03/2010 12:40 AM
255 SystemPerl Closed Normal rt57469: Parallel build fails Wilson Snyder 05/24/2010 02:04 PM
582 Verilog-Perl Closed Normal rt81501: Test failures due to hash randomisation in perl 5.17.6 Wilson Snyder 11/28/2012 01:47 PM
(26-50/73) Per page: 25, 100

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