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# Project Status Priority Subject Assignee Updated
153 Verilog-Perl Closed Normal Verilog Perl does not parse widths correctly Wilson Snyder 12/09/2010 11:09 PM
154 Verilog-Perl Closed Normal Error making Verilog-Perl-3.011 Wilson Snyder 02/08/2009 09:10 AM
155 Verilog-Perl Closed Normal Verilog packages Error Wilson Snyder 04/07/2009 06:36 AM
157 Verilog-Perl Closed Normal typo in VParseLex.l Wilson Snyder 12/04/2007 11:30 AM
158 Verilog-Perl Closed Normal macro with systemVerilog lexical delimiter fails if white spaces present in macro calling Wilson Snyder 03/27/2008 10:38 AM
159 Verilog-Perl Closed Normal Bug in Verilog-Perl: rand Wilson Snyder 03/31/2008 05:41 PM
160 Verilog-Perl Closed Normal Bug in Verilog-Perl - MIN:TYP:MAX delays in assign Wilson Snyder 03/31/2008 05:05 PM
161 Verilog-Perl Closed Normal Output Register init value Wilson Snyder 04/14/2008 05:14 PM
162 Verilog-Perl Closed Normal nested macros are not expanded correctly if a macro has arguments ... Wilson Snyder 02/08/2009 09:14 AM
164 Verilog-Perl Closed Normal Test 04critic written badly Wilson Snyder 09/29/2008 01:48 PM
191 Verilog-Perl Closed Normal Define with formal matching $pli call gets misexpanded Wilson Snyder 11/24/2009 02:58 PM
200 Verilog-Perl Closed Normal Support modports in interfaces Wilson Snyder 01/21/2010 09:23 PM
222 Verilog-Perl Closed Normal An example in Verilog::EditFiles doesn't work Wilson Snyder 03/29/2010 06:54 PM
282 Verilog-Perl Closed Normal Escaped identifiers that are keywords are unescaped Wilson Snyder 09/20/2010 07:32 PM
459 Verilog-Perl Closed Normal Comment starting line number wrong Wilson Snyder 05/04/2012 09:51 PM
582 Verilog-Perl Closed Normal rt81501: Test failures due to hash randomisation in perl 5.17.6 Wilson Snyder 11/28/2012 01:47 PM
109 Vregs Closed Normal Autogenerated code produces incorrect C/C++ syntax Wilson Snyder 02/25/2009 04:29 PM
1537 Verilator Feature Low Support FST structure tracing w/GTKwave 10/06/2019 12:31 PM
1637 Verilator Feature Low Support $displayb/o/h, $writeb/o/h (starter project) 12/15/2019 01:38 AM
1638 Verilator Feature Low Support $ferror/$fflush (starter task) 12/15/2019 01:40 AM
1639 Verilator Feature Low Support $countbits (starter task) 12/15/2019 01:42 AM
1580 Verilator Closed Low test_regress/t_prot_lib is unstable Todd Strader 11/05/2019 01:51 PM
1544 Verilator Closed Low Improve readme Wilson Snyder 11/08/2019 03:34 AM
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