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# Project Status Priority Subject Assignee Updated
112 IPC::Locker Closed Normal t/02_help.t incompatibility with Pod::Usage 1.30 Wilson Snyder 02/08/2009 09:08 AM
164 Verilog-Perl Closed Normal Test 04critic written badly Wilson Snyder 09/29/2008 01:48 PM
1 TestProject Closed Normal Example issue 04/16/2008 11:13 PM
161 Verilog-Perl Closed Normal Output Register init value Wilson Snyder 04/14/2008 05:14 PM
159 Verilog-Perl Closed Normal Bug in Verilog-Perl: rand Wilson Snyder 03/31/2008 05:41 PM
160 Verilog-Perl Closed Normal Bug in Verilog-Perl - MIN:TYP:MAX delays in assign Wilson Snyder 03/31/2008 05:05 PM
158 Verilog-Perl Closed Normal macro with systemVerilog lexical delimiter fails if white spaces present in macro calling Wilson Snyder 03/27/2008 10:38 AM
157 Verilog-Perl Closed Normal typo in VParseLex.l Wilson Snyder 12/04/2007 11:30 AM
129 Verilog-Perl Closed Normal wire declaration is wrong when add new net Wilson Snyder 01/25/2007 03:27 PM
125 Verilog-Perl Closed Normal Failure to correctly parse buses of concatenated bits Wilson Snyder 01/09/2007 11:36 AM
124 Verilog-Perl Closed Normal Spurious parse errors with a file with many blank lines Wilson Snyder 02/04/2005 04:34 PM
123 Verilog-Perl Closed Normal directories return in resolve_filename instead of filenames 01/27/2005 11:23 AM
1629 Verilator WillNotFix Normal Optimize wide vectors to use 64 bit entries Wilson Snyder 12/09/2019 02:55 AM
114 IPC::Locker NoFixNeeded Normal Locking issues Wilson Snyder 09/19/2009 07:47 AM
120 Verilog-Perl NoFixNeeded Normal syntax error, unexpected "do", expecting "IDENTIFIER" Wilson Snyder 07/31/2008 07:49 AM
121 Verilog-Perl NotEnoughInfo Normal Error building Verilog-Perl 3.121 Wilson Snyder 06/01/2009 09:45 PM
119 Verilog-Perl NotEnoughInfo Normal MacOSX 10.4 installation Wilson Snyder 04/14/2008 05:15 PM
1639 Verilator Feature Low Support $countbits (starter task) 12/15/2019 01:42 AM
1638 Verilator Feature Low Support $ferror/$fflush (starter task) 12/15/2019 01:40 AM
1637 Verilator Feature Low Support $displayb/o/h, $writeb/o/h (starter project) 12/15/2019 01:38 AM
1537 Verilator Feature Low Support FST structure tracing w/GTKwave 10/06/2019 12:31 PM
1544 Verilator Closed Low Improve readme Wilson Snyder 11/08/2019 03:34 AM
1580 Verilator Closed Low test_regress/t_prot_lib is unstable Todd Strader 11/05/2019 01:51 PM
(51-73/73) Per page: 25, 100

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