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# Project Status Priority Subject Assignee Updated
379 Verilator Feature Normal Support dynamic memory new and delete 03/02/2012 11:42 PM
173 Verilator Closed Normal Support enums Wilson Snyder 02/07/2010 12:40 PM
1538 Verilator Feature Normal Support full UVM parsing and XML dump 10/06/2019 01:26 PM
200 Verilog-Perl Closed Normal Support modports in interfaces Wilson Snyder 01/21/2010 09:23 PM
378 Verilator Feature Normal Support properties and assertions 03/02/2012 11:42 PM
181 Verilator Closed Normal Support struct and union Wilson Snyder 07/31/2012 10:53 PM
1541 Verilator Feature Normal Support unpacked structs 10/06/2019 01:24 PM
382 Verilog-mode Closed Normal Support UVM Wilson Snyder 09/07/2011 04:34 PM
120 Verilog-Perl NoFixNeeded Normal syntax error, unexpected "do", expecting "IDENTIFIER" Wilson Snyder 07/31/2008 07:49 AM
112 IPC::Locker Closed Normal t/02_help.t incompatibility with Pod::Usage 1.30 Wilson Snyder 02/08/2009 09:08 AM
164 Verilog-Perl Closed Normal Test 04critic written badly Wilson Snyder 09/29/2008 01:48 PM
1618 Verilator Closed Normal Travis Mail not going to authors? Todd Strader 12/07/2019 04:35 PM
157 Verilog-Perl Closed Normal typo in VParseLex.l Wilson Snyder 12/04/2007 11:30 AM
296 Verilog-mode Closed Normal Use derived-mode prog-mode? 12/14/2010 09:36 PM
155 Verilog-Perl Closed Normal Verilog packages Error Wilson Snyder 04/07/2009 06:36 AM
153 Verilog-Perl Closed Normal Verilog Perl does not parse widths correctly Wilson Snyder 12/09/2010 11:09 PM
129 Verilog-Perl Closed Normal wire declaration is wrong when add new net Wilson Snyder 01/25/2007 03:27 PM
1544 Verilator Closed Low Improve readme Wilson Snyder 11/08/2019 03:34 AM
1639 Verilator Feature Low Support $countbits (starter task) 12/15/2019 01:42 AM
1637 Verilator Feature Low Support $displayb/o/h, $writeb/o/h (starter project) 12/15/2019 01:38 AM
1638 Verilator Feature Low Support $ferror/$fflush (starter task) 12/15/2019 01:40 AM
1537 Verilator Feature Low Support FST structure tracing w/GTKwave 10/06/2019 12:31 PM
1580 Verilator Closed Low test_regress/t_prot_lib is unstable Todd Strader 11/05/2019 01:51 PM
(51-73/73) Per page: 25, 100

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