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# Project Status Priority Subject Assignee Updated
106 Verilog-Perl Closed Normal Fix escaped identifiers in preprocessor 09/30/2009 04:03 PM
125 Verilog-Perl Closed Normal Failure to correctly parse buses of concatenated bits Wilson Snyder 01/09/2007 11:36 AM
1 TestProject Closed Normal Example issue 04/16/2008 11:13 PM
282 Verilog-Perl Closed Normal Escaped identifiers that are keywords are unescaped Wilson Snyder 09/20/2010 07:32 PM
154 Verilog-Perl Closed Normal Error making Verilog-Perl-3.011 Wilson Snyder 02/08/2009 09:10 AM
121 Verilog-Perl NotEnoughInfo Normal Error building Verilog-Perl 3.121 Wilson Snyder 06/01/2009 09:45 PM
955 Verilog-mode Confirmed Normal End mis-indents with sized replication 03/26/2018 08:48 PM
621 Verilator Closed Normal Enable duplicate gate elimination in ~3.848. 06/02/2013 06:54 PM
123 Verilog-Perl Closed Normal directories return in resolve_filename instead of filenames 01/27/2005 11:23 AM
191 Verilog-Perl Closed Normal Define with formal matching $pli call gets misexpanded Wilson Snyder 11/24/2009 02:58 PM
1200 Verilog-Perl Closed Normal Concat parsing issue 09/09/2017 01:56 AM
1606 Verilator Resolved Normal Complete string methods (starter project) 12/15/2019 01:14 PM
459 Verilog-Perl Closed Normal Comment starting line number wrong Wilson Snyder 05/04/2012 09:51 PM
1567 Verilator Feature Normal Cocotb Integration 12/22/2019 08:02 PM
1607 Verilator Closed Normal CI: Add gtkwave include diff to extended tests Wilson Snyder 11/19/2019 03:11 AM
159 Verilog-Perl Closed Normal Bug in Verilog-Perl: rand Wilson Snyder 03/31/2008 05:41 PM
160 Verilog-Perl Closed Normal Bug in Verilog-Perl - MIN:TYP:MAX delays in assign Wilson Snyder 03/31/2008 05:05 PM
270 Verilog-mode Closed Normal AUTOINST and SystemVerilog interfaces Wilson Snyder 08/18/2010 02:19 PM
109 Vregs Closed Normal Autogenerated code produces incorrect C/C++ syntax Wilson Snyder 02/25/2009 04:29 PM
95 Verilog-mode Closed Normal Attributes indent incorrectly Michael McNamara 03/31/2010 05:28 PM
222 Verilog-Perl Closed Normal An example in Verilog::EditFiles doesn't work Wilson Snyder 03/29/2010 06:54 PM
174 Verilator Closed Normal Add support for typedef Wilson Snyder 02/07/2010 12:41 PM
604 Verilator Closed Normal -x-initial-edge breaks with logic bug fix Jeremy Bennett 01/17/2013 12:21 PM
(51-73/73) Per page: 25, 100

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