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#
Project
Status
Priority
Subject
Assignee
Updated
1657
Verilator
New
Normal
Investigate google build?
Todd Strader
12/21/2019 03:36 PM
1650
Verilator
Feature
Normal
Implement type_reference (medium starter task)
12/20/2019 01:23 AM
1639
Verilator
Feature
Low
Support $countbits (starter task)
12/15/2019 01:42 AM
1638
Verilator
Feature
Low
Support $ferror/$fflush (starter task)
12/15/2019 01:40 AM
1637
Verilator
Feature
Low
Support $displayb/o/h, $writeb/o/h (starter project)
12/15/2019 01:38 AM
1567
Verilator
Feature
Normal
Cocotb Integration
12/22/2019 08:02 PM
1543
Verilator
Feature
Normal
Improve performance of icache
10/06/2019 01:23 PM
1542
Verilator
Feature
Normal
Improve performance of bit operations by vectorizing
10/06/2019 01:24 PM
1541
Verilator
Feature
Normal
Support unpacked structs
10/06/2019 01:24 PM
1540
Verilator
Feature
Normal
Improve internal elaboration algorithm
10/06/2019 01:00 PM
1539
Verilator
Feature
Normal
Improve internals of inliner
10/06/2019 12:54 PM
1538
Verilator
Feature
Normal
Support full UVM parsing and XML dump
10/06/2019 01:26 PM
1537
Verilator
Feature
Low
Support FST structure tracing w/GTKwave
10/06/2019 12:31 PM
379
Verilator
Feature
Normal
Support dynamic memory new and delete
03/02/2012 11:42 PM
378
Verilator
Feature
Normal
Support properties and assertions
03/02/2012 11:42 PM
377
Verilator
Feature
Normal
Support classes and methods
02/06/2016 11:16 PM
1628
Verilator
Confirmed
Normal
Ongoing cleanup of SymbiFlow sv-tests (help wanted)
12/15/2019 10:41 PM
1566
Verilator
Confirmed
Normal
FST dumping is slow
10/17/2019 10:39 PM
955
Verilog-mode
Confirmed
Normal
End mis-indents with sized replication
03/26/2018 08:48 PM
838
Verilog-mode
Confirmed
Normal
randsequence misindented
11/19/2017 01:17 PM
1606
Verilator
Resolved
Normal
Complete string methods (starter project)
12/15/2019 01:14 PM
1200
Verilog-Perl
Closed
Normal
Concat parsing issue
09/09/2017 01:56 AM
621
Verilator
Closed
Normal
Enable duplicate gate elimination in ~3.848.
06/02/2013 06:54 PM
296
Verilog-mode
Closed
Normal
Use derived-mode prog-mode?
12/14/2010 09:36 PM
123
Verilog-Perl
Closed
Normal
directories return in resolve_filename instead of filenames
01/27/2005 11:23 AM
106
Verilog-Perl
Closed
Normal
Fix escaped identifiers in preprocessor
09/30/2009 04:03 PM
1
TestProject
Closed
Normal
Example issue
04/16/2008 11:13 PM
604
Verilator
Closed
Normal
-x-initial-edge breaks with logic bug fix
Jeremy Bennett
01/17/2013 12:21 PM
218
Verilog-mode
Closed
Normal
pure virtual indentation
Michael McNamara
06/03/2010 12:40 AM
180
Verilog-mode
Closed
Normal
Struct pack signed misindents
Michael McNamara
12/10/2009 11:48 AM
95
Verilog-mode
Closed
Normal
Attributes indent incorrectly
Michael McNamara
03/31/2010 05:28 PM
1618
Verilator
Closed
Normal
Travis Mail not going to authors?
Todd Strader
12/07/2019 04:35 PM
1580
Verilator
Closed
Low
test_regress/t_prot_lib is unstable
Todd Strader
11/05/2019 01:51 PM
1487
Verilator
Closed
Normal
New WIDTH warnings on genvars
Todd Strader
08/29/2019 11:15 PM
1607
Verilator
Closed
Normal
CI: Add gtkwave include diff to extended tests
Wilson Snyder
11/19/2019 03:11 AM
1544
Verilator
Closed
Low
Improve readme
Wilson Snyder
11/08/2019 03:34 AM
1248
Verilator
Closed
Normal
Large structures expose GCC/clang compile time bug
Wilson Snyder
01/02/2018 11:14 PM
1174
Verilator
Closed
Normal
Shift gives VL_SHIFTR_IIW not declared
Wilson Snyder
06/22/2017 10:37 PM
582
Verilog-Perl
Closed
Normal
rt81501: Test failures due to hash randomisation in perl 5.17.6
Wilson Snyder
11/28/2012 01:47 PM
459
Verilog-Perl
Closed
Normal
Comment starting line number wrong
Wilson Snyder
05/04/2012 09:51 PM
382
Verilog-mode
Closed
Normal
Support UVM
Wilson Snyder
09/07/2011 04:34 PM
376
Verilator
Closed
Normal
Support "parameter type"
Wilson Snyder
05/19/2016 01:17 AM
282
Verilog-Perl
Closed
Normal
Escaped identifiers that are keywords are unescaped
Wilson Snyder
09/20/2010 07:32 PM
270
Verilog-mode
Closed
Normal
AUTOINST and SystemVerilog interfaces
Wilson Snyder
08/18/2010 02:19 PM
255
SystemPerl
Closed
Normal
rt57469: Parallel build fails
Wilson Snyder
05/24/2010 02:04 PM
222
Verilog-Perl
Closed
Normal
An example in Verilog::EditFiles doesn't work
Wilson Snyder
03/29/2010 06:54 PM
200
Verilog-Perl
Closed
Normal
Support modports in interfaces
Wilson Snyder
01/21/2010 09:23 PM
191
Verilog-Perl
Closed
Normal
Define with formal matching $pli call gets misexpanded
Wilson Snyder
11/24/2009 02:58 PM
181
Verilator
Closed
Normal
Support struct and union
Wilson Snyder
07/31/2012 10:53 PM
174
Verilator
Closed
Normal
Add support for typedef
Wilson Snyder
02/07/2010 12:41 PM
173
Verilator
Closed
Normal
Support enums
Wilson Snyder
02/07/2010 12:40 PM
164
Verilog-Perl
Closed
Normal
Test 04critic written badly
Wilson Snyder
09/29/2008 01:48 PM
162
Verilog-Perl
Closed
Normal
nested macros are not expanded correctly if a macro has arguments ...
Wilson Snyder
02/08/2009 09:14 AM
161
Verilog-Perl
Closed
Normal
Output Register init value
Wilson Snyder
04/14/2008 05:14 PM
160
Verilog-Perl
Closed
Normal
Bug in Verilog-Perl - MIN:TYP:MAX delays in assign
Wilson Snyder
03/31/2008 05:05 PM
159
Verilog-Perl
Closed
Normal
Bug in Verilog-Perl: rand
Wilson Snyder
03/31/2008 05:41 PM
158
Verilog-Perl
Closed
Normal
macro with systemVerilog lexical delimiter fails if white spaces present in macro calling
Wilson Snyder
03/27/2008 10:38 AM
157
Verilog-Perl
Closed
Normal
typo in VParseLex.l
Wilson Snyder
12/04/2007 11:30 AM
155
Verilog-Perl
Closed
Normal
Verilog packages Error
Wilson Snyder
04/07/2009 06:36 AM
154
Verilog-Perl
Closed
Normal
Error making Verilog-Perl-3.011
Wilson Snyder
02/08/2009 09:10 AM
153
Verilog-Perl
Closed
Normal
Verilog Perl does not parse widths correctly
Wilson Snyder
12/09/2010 11:09 PM
129
Verilog-Perl
Closed
Normal
wire declaration is wrong when add new net
Wilson Snyder
01/25/2007 03:27 PM
125
Verilog-Perl
Closed
Normal
Failure to correctly parse buses of concatenated bits
Wilson Snyder
01/09/2007 11:36 AM
124
Verilog-Perl
Closed
Normal
Spurious parse errors with a file with many blank lines
Wilson Snyder
02/04/2005 04:34 PM
113
IPC::Locker
Closed
Normal
pidwatch issue on cygwin-thread-multi-64int
Wilson Snyder
02/08/2009 09:09 AM
112
IPC::Locker
Closed
Normal
t/02_help.t incompatibility with Pod::Usage 1.30
Wilson Snyder
02/08/2009 09:08 AM
109
Vregs
Closed
Normal
Autogenerated code produces incorrect C/C++ syntax
Wilson Snyder
02/25/2009 04:29 PM
99
Verilator
Closed
Normal
Internal error on case statement with identical cases.
Wilson Snyder
06/23/2009 11:05 PM
1629
Verilator
WillNotFix
Normal
Optimize wide vectors to use 64 bit entries
Wilson Snyder
12/09/2019 02:55 AM
120
Verilog-Perl
NoFixNeeded
Normal
syntax error, unexpected "do", expecting "IDENTIFIER"
Wilson Snyder
07/31/2008 07:49 AM
114
IPC::Locker
NoFixNeeded
Normal
Locking issues
Wilson Snyder
09/19/2009 07:47 AM
121
Verilog-Perl
NotEnoughInfo
Normal
Error building Verilog-Perl 3.121
Wilson Snyder
06/01/2009 09:45 PM
119
Verilog-Perl
NotEnoughInfo
Normal
MacOSX 10.4 installation
Wilson Snyder
04/14/2008 05:15 PM
(1-73/73)
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