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# Project Status Priority Subject Assignee Updated
1629 Verilator WillNotFix Normal Optimize wide vectors to use 64 bit entries Wilson Snyder 12/09/2019 02:55 AM
1607 Verilator Closed Normal CI: Add gtkwave include diff to extended tests Wilson Snyder 11/19/2019 03:11 AM
1544 Verilator Closed Low Improve readme Wilson Snyder 11/08/2019 03:34 AM
1248 Verilator Closed Normal Large structures expose GCC/clang compile time bug Wilson Snyder 01/02/2018 11:14 PM
1174 Verilator Closed Normal Shift gives VL_SHIFTR_IIW not declared Wilson Snyder 06/22/2017 10:37 PM
582 Verilog-Perl Closed Normal rt81501: Test failures due to hash randomisation in perl 5.17.6 Wilson Snyder 11/28/2012 01:47 PM
459 Verilog-Perl Closed Normal Comment starting line number wrong Wilson Snyder 05/04/2012 09:51 PM
382 Verilog-mode Closed Normal Support UVM Wilson Snyder 09/07/2011 04:34 PM
376 Verilator Closed Normal Support "parameter type" Wilson Snyder 05/19/2016 01:17 AM
282 Verilog-Perl Closed Normal Escaped identifiers that are keywords are unescaped Wilson Snyder 09/20/2010 07:32 PM
270 Verilog-mode Closed Normal AUTOINST and SystemVerilog interfaces Wilson Snyder 08/18/2010 02:19 PM
255 SystemPerl Closed Normal rt57469: Parallel build fails Wilson Snyder 05/24/2010 02:04 PM
222 Verilog-Perl Closed Normal An example in Verilog::EditFiles doesn't work Wilson Snyder 03/29/2010 06:54 PM
200 Verilog-Perl Closed Normal Support modports in interfaces Wilson Snyder 01/21/2010 09:23 PM
191 Verilog-Perl Closed Normal Define with formal matching $pli call gets misexpanded Wilson Snyder 11/24/2009 02:58 PM
181 Verilator Closed Normal Support struct and union Wilson Snyder 07/31/2012 10:53 PM
174 Verilator Closed Normal Add support for typedef Wilson Snyder 02/07/2010 12:41 PM
173 Verilator Closed Normal Support enums Wilson Snyder 02/07/2010 12:40 PM
164 Verilog-Perl Closed Normal Test 04critic written badly Wilson Snyder 09/29/2008 01:48 PM
162 Verilog-Perl Closed Normal nested macros are not expanded correctly if a macro has arguments ... Wilson Snyder 02/08/2009 09:14 AM
161 Verilog-Perl Closed Normal Output Register init value Wilson Snyder 04/14/2008 05:14 PM
160 Verilog-Perl Closed Normal Bug in Verilog-Perl - MIN:TYP:MAX delays in assign Wilson Snyder 03/31/2008 05:05 PM
159 Verilog-Perl Closed Normal Bug in Verilog-Perl: rand Wilson Snyder 03/31/2008 05:41 PM
158 Verilog-Perl Closed Normal macro with systemVerilog lexical delimiter fails if white spaces present in macro calling Wilson Snyder 03/27/2008 10:38 AM
157 Verilog-Perl Closed Normal typo in VParseLex.l Wilson Snyder 12/04/2007 11:30 AM
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