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# Project Status Priority Subject Assignee Updated
1657 Verilator New Normal Investigate google build? Todd Strader 12/21/2019 03:36 PM
1567 Verilator Feature Normal Cocotb Integration 12/22/2019 08:02 PM
1650 Verilator Feature Normal Implement type_reference (medium starter task) 12/20/2019 01:23 AM
1540 Verilator Feature Normal Improve internal elaboration algorithm 10/06/2019 01:00 PM
1539 Verilator Feature Normal Improve internals of inliner 10/06/2019 12:54 PM
1542 Verilator Feature Normal Improve performance of bit operations by vectorizing 10/06/2019 01:24 PM
1543 Verilator Feature Normal Improve performance of icache 10/06/2019 01:23 PM
377 Verilator Feature Normal Support classes and methods 02/06/2016 11:16 PM
379 Verilator Feature Normal Support dynamic memory new and delete 03/02/2012 11:42 PM
1538 Verilator Feature Normal Support full UVM parsing and XML dump 10/06/2019 01:26 PM
378 Verilator Feature Normal Support properties and assertions 03/02/2012 11:42 PM
1541 Verilator Feature Normal Support unpacked structs 10/06/2019 01:24 PM
955 Verilog-mode Confirmed Normal End mis-indents with sized replication 03/26/2018 08:48 PM
1566 Verilator Confirmed Normal FST dumping is slow 10/17/2019 10:39 PM
1628 Verilator Confirmed Normal Ongoing cleanup of SymbiFlow sv-tests (help wanted) 12/15/2019 10:41 PM
838 Verilog-mode Confirmed Normal randsequence misindented 11/19/2017 01:17 PM
1606 Verilator Resolved Normal Complete string methods (starter project) 12/15/2019 01:14 PM
604 Verilator Closed Normal -x-initial-edge breaks with logic bug fix Jeremy Bennett 01/17/2013 12:21 PM
174 Verilator Closed Normal Add support for typedef Wilson Snyder 02/07/2010 12:41 PM
222 Verilog-Perl Closed Normal An example in Verilog::EditFiles doesn't work Wilson Snyder 03/29/2010 06:54 PM
95 Verilog-mode Closed Normal Attributes indent incorrectly Michael McNamara 03/31/2010 05:28 PM
109 Vregs Closed Normal Autogenerated code produces incorrect C/C++ syntax Wilson Snyder 02/25/2009 04:29 PM
270 Verilog-mode Closed Normal AUTOINST and SystemVerilog interfaces Wilson Snyder 08/18/2010 02:19 PM
160 Verilog-Perl Closed Normal Bug in Verilog-Perl - MIN:TYP:MAX delays in assign Wilson Snyder 03/31/2008 05:05 PM
159 Verilog-Perl Closed Normal Bug in Verilog-Perl: rand Wilson Snyder 03/31/2008 05:41 PM
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