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# Project Status Priority Subject Assignee Updated
1629 Verilator WillNotFix Normal Optimize wide vectors to use 64 bit entries Wilson Snyder 12/09/2019 02:55 AM
1628 Verilator Confirmed Normal Ongoing cleanup of SymbiFlow sv-tests (help wanted) 12/08/2019 01:07 PM
1618 Verilator Closed Normal Travis Mail not going to authors? Todd Strader 12/07/2019 04:35 PM
1607 Verilator Closed Normal CI: Add gtkwave include diff to extended tests Wilson Snyder 11/19/2019 03:11 AM
1606 Verilator Assigned Normal Complete string methods (starter project) 12/10/2019 11:17 AM
1580 Verilator Closed Low test_regress/t_prot_lib is unstable Todd Strader 11/05/2019 01:51 PM
1567 Verilator Feature Normal Cocotb Integration 12/13/2019 03:50 PM
1566 Verilator Confirmed Normal FST dumping is slow 10/17/2019 10:39 PM
1544 Verilator Closed Low Improve readme Wilson Snyder 11/08/2019 03:34 AM
1543 Verilator Feature Normal Improve performance of icache 10/06/2019 01:23 PM
1542 Verilator Feature Normal Improve performance of bit operations by vectorizing 10/06/2019 01:24 PM
1541 Verilator Feature Normal Support unpacked structs 10/06/2019 01:24 PM
1540 Verilator Feature Normal Improve internal elaboration algorithm 10/06/2019 01:00 PM
1539 Verilator Feature Normal Improve internals of inliner 10/06/2019 12:54 PM
1538 Verilator Feature Normal Support full UVM parsing and XML dump 10/06/2019 01:26 PM
1537 Verilator Feature Low Support FST structure tracing w/GTKwave 10/06/2019 12:31 PM
1487 Verilator Closed Normal New WIDTH warnings on genvars Todd Strader 08/29/2019 11:15 PM
1248 Verilator Closed Normal Large structures expose GCC/clang compile time bug Wilson Snyder 01/02/2018 11:14 PM
1200 Verilog-Perl Closed Normal Concat parsing issue 09/09/2017 01:56 AM
1174 Verilator Closed Normal Shift gives VL_SHIFTR_IIW not declared Wilson Snyder 06/22/2017 10:37 PM
955 Verilog-mode Confirmed Normal End mis-indents with sized replication Alex Reed 03/26/2018 08:48 PM
838 Verilog-mode Confirmed Normal randsequence misindented 11/19/2017 01:17 PM
621 Verilator Closed Normal Enable duplicate gate elimination in ~3.848. 06/02/2013 06:54 PM
604 Verilator Closed Normal -x-initial-edge breaks with logic bug fix Jeremy Bennett 01/17/2013 12:21 PM
582 Verilog-Perl Closed Normal rt81501: Test failures due to hash randomisation in perl 5.17.6 Wilson Snyder 11/28/2012 01:47 PM
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