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# Project Status Priority Subject Assignee Updated
1471 Verilog-mode Closed Normal Describe how to find source file to debug autos Wilson Snyder 06/21/2019 09:52 PM
1453 Verilog-mode Feature Normal AUTOLOGIC/AUTOINST for unpacked array signal input to submodule 10/18/2019 02:24 AM
1452 Verilog-mode NoFixNeeded Normal Use AUTO_TEMPLATE number from instance name to control string in port signalname Wilson Snyder 06/01/2019 12:46 AM
1416 Verilog-mode NoFixNeeded Normal problems getting Verilog-batch-auto to work with library file Wilson Snyder 04/09/2019 08:23 PM
1401 Verilog-mode Closed Normal AUTOREGINPUT does work if signal is on LHS of assign statement Wilson Snyder 03/08/2019 02:21 AM
1379 Verilog-mode Closed Normal problem with autotemplate regex with capture group reference Wilson Snyder 01/02/2019 11:02 PM
1323 Verilog-mode NoFixNeeded Normal verilog-mode specific faces? 07/12/2018 11:10 AM
1313 Verilog-mode Confirmed Normal AUTOINST problem for module containing clocking block 07/15/2019 07:07 PM
1310 Verilog-mode WillNotFix Low add date/time stamp to comment 05/19/2018 11:22 AM
1253 Verilog-mode Closed Normal AUTOINST broken for parameterized interface port Wilson Snyder 12/21/2017 07:09 PM
1237 Verilog-mode Closed Normal "end" not indented correctly after replication with variable number Alex Reed 11/13/2017 09:00 PM
1100 Verilog-mode NoFixNeeded Normal AUTOINSTPARAM work for interfaces? Wilson Snyder 10/31/2016 07:42 PM
1072 Verilog-mode Closed Normal randcase not indenting correctly Wilson Snyder 07/24/2016 12:09 PM
669 Verilog-mode Closed Normal verilog-label-be function doesn't implement &optional arg 07/29/2013 07:49 PM
626 Verilog-mode Closed High problem/question for AUTOLOGIC of array with different elements going to different instances 11/10/2013 03:17 PM
612 Verilog-mode Closed High confused using AUTO_TEMPLATE with regexp for instance name and pin name Wilson Snyder 02/04/2013 07:32 PM
390 Verilog-mode Closed Normal Indenting of user-defined data types Michael McNamara 11/29/2011 02:05 PM
386 Verilog-mode Feature Normal Indenting of user-defined data types 07/23/2019 01:05 AM
373 Verilog-mode Closed Normal AUTO problems with ports of type array of structures Wilson Snyder 08/09/2011 11:32 PM
345 Verilog-mode Closed High can't get untabify on save to work 12/16/2015 12:58 AM
245 Verilog-mode Closed Normal .PORT System Verilog autoinst naming Wilson Snyder 04/20/2010 02:40 PM
75 Verilog-mode Closed Normal support SV instances in port list with AUTOs Wilson Snyder 12/10/2009 11:47 AM

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