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# Project Status Priority Subject Assignee Updated
1352 Verilator WillNotFix Normal Do you have plan to use CMake to replace current autoconf? 10/24/2018 07:25 PM
1307 Verilator NotEnoughInfo Normal Can not dump trace with CMAKE compiled SystemC library Enzo Chi 05/24/2019 08:03 AM
1272 Verilog-mode Confirmed Normal alignment and indentation issue with import and "=" for localparam 02/02/2018 12:30 AM
1268 Verilator Closed High tracing_x examples do not generate proper waveform with verilator 3.918 Wilson Snyder 02/02/2018 01:16 AM
1256 Verilator Duplicate High example/trace_sc doesn't compile with SystemC 2.3.2 01/01/2018 10:06 PM
1249 Verilator NotEnoughInfo Normal Struct initialisation with data type and member name is not supported in 3.916 08/25/2018 02:41 PM
1192 Verilator WillNotFix Normal Can't override parameter defined as "type xxxx" through command line with "-G" 11/18/2017 10:56 PM
1168 Verilog-mode Feature Normal Is it possible to make "begin" keyword align with case expression? 11/30/2017 06:36 AM
1167 Verilog-mode Confirmed Normal Port list is not aligned properly when the first port declaration is not start from a new line 11/19/2017 01:38 PM
1164 Verilator Closed Urgent Failed generate C++ code with unique casez when "--assert" argument Wilson Snyder 05/31/2017 02:07 AM
1117 Verilator Closed High Can't compile with "--assert" for files with "unique casez" Wilson Snyder 05/17/2017 01:42 AM
1000 Verilog-mode Duplicate Normal "class" inside "interface" is not indent 11/19/2017 01:29 PM
960 Verilog-mode Confirmed Normal Restart alignment after empty or comments lines 11/19/2017 01:27 PM
928 Verilog-mode Closed Normal Wrong indent on 'typedef' and 'virtual class' Alex Reed 06/26/2015 11:08 PM
905 Verilog-mode Closed Normal labeled 'assert' is not aligned properly Alex Reed 03/27/2015 03:14 PM
817 Verilog-mode Closed Normal Wrong alignment on 'virtual' keyword 07/21/2015 02:30 AM

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