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# Project Status Priority Subject Assignee Updated
1518 Verilator Feature Normal Protect against --protect-lib Verilator runtime incompatibility Todd Strader 10/06/2019 01:27 PM
1517 Verilator Feature Normal Add support for additional simulators in --protect-lib Todd Strader 10/06/2019 01:27 PM
1516 Verilog-mode Confirmed Normal Wrong indentation after SV streaming statement 12/21/2019 03:15 PM
1515 Verilator Feature Low VPI: Log all variables that were accessed Stefan Wallentowitz 12/22/2019 08:05 PM
1514 Verilator Feature Low Switch for file to read public signals from Stefan Wallentowitz 12/22/2019 08:05 PM
1501 Verilator Confirmed Normal Support bind statements within generate blocks 12/22/2019 08:06 PM
1495 Verilog-mode Confirmed Normal Wrong statement continue alignment. 09/15/2019 03:40 PM
1489 Verilator Feature Normal Python support for Verilated designs Maarten De Braekeleer 12/22/2019 08:06 PM
1482 Verilator Feature Normal Conditional event controls ("iff") 12/22/2019 08:07 PM
1479 Verilator Feature Normal Feature Request: VerilatedVcd callback on rolloverMB Marc Jessome 12/22/2019 08:07 PM
1478 Verilator Confirmed Normal -faligned-new does not work under Travis with clang 07/18/2019 12:02 PM
1477 Verilator Assigned Normal Add macOS coverage in Travis CI 07/18/2019 10:33 AM
1470 Verilator Feature Low VPI systemtf Stefan Wallentowitz 09/26/2019 12:39 PM
1454 Verilator Feature Normal Support for loop index into generated arrays 12/22/2019 08:09 PM
1453 Verilog-mode Feature Normal AUTOLOGIC/AUTOINST for unpacked array signal input to submodule 10/18/2019 02:24 AM
1447 Verilog-mode Feature Normal Expand AUTOINST default values for parameters 05/29/2019 10:46 PM
1446 Verilog-mode Confirmed Normal SystemVerilog interface indentation in module declaration 05/29/2019 10:49 PM
1430 Verilator AskedReporter Normal Broken node on indexed interface modport Wilson Snyder 12/22/2019 08:09 PM
1404 Verilog-mode Confirmed Normal alignment within generate-if 03/03/2019 12:55 AM
1395 Verilator Feature Normal Extend UNUSED to flag signals which are not in the cone of a module output 12/22/2019 08:10 PM
1382 Verilator AskedReporter Normal Inconsistent LITENDIAN warnings on arrays 12/22/2019 08:10 PM
1373 Verilator Feature Normal Cannot write to top-level tristate ports 12/22/2019 08:11 PM
1369 Verilator Confirmed Normal Raise error / warning on continous assignment to reg Wilson Snyder 12/22/2019 08:11 PM
1366 Verilator AskedReporter Normal Large increase in design header file with threads and tracing 11/29/2018 11:13 PM
1321 Verilog-mode Confirmed Normal indentation of coverpoint is incorrect if coverpoint expression is a concatenation 12/21/2019 03:16 PM
(51-75/162) Per page: 25, 100, 250

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