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# Project Status Priority Subject Assignee Updated
1664 Verilator New Normal Verilator Generates C++ code which does not compile ... 04/27/2020 01:04 PM
1663 Verilator New Normal Verilator Generates C++ code which does not compile ... 04/27/2020 07:31 AM
1659 Verilog-Perl Resolved Normal Preprocessor doesn't handle one case of definition substitution properly Wilson Snyder 01/11/2020 02:16 PM
1657 Verilator New Normal Investigate google build? Todd Strader 12/21/2019 03:36 PM
1656 Verilator Assigned Normal [RFC] Relaxing UNOPTFLAT by dividing unpacked array Yutetsu TAKATSUKASA 12/21/2019 03:01 PM
1655 Verilator Assigned Normal Build support for Windows. Kuba Ober 12/21/2019 02:35 PM
1650 Verilator Feature Normal Implement type_reference (medium starter task) 12/20/2019 01:23 AM
1649 Verilator Feature Low Lint filter specific warnings or wildcards/regexp 12/22/2019 07:51 PM
1647 Verilator Feature Low Queues in other unpacked arrays Stefan Wallentowitz 12/22/2019 07:52 PM
1646 Verilator New Low $bits for dynamic/runtime usage Stefan Wallentowitz 12/22/2019 07:53 PM
1644 Verilator Confirmed Normal Performance delta between 4.020 and 4.022 12/22/2019 07:53 PM
1643 Verilator Resolved Normal Foreach of dynamic sized queue Stefan Wallentowitz 12/18/2019 11:33 PM
1642 Verilator New Low Check for proper array sizes Stefan Wallentowitz 12/22/2019 07:55 PM
1641 Verilator Resolved Normal Statement queue pop_front error after foreach 12/17/2019 11:10 AM
1640 Verilator Assigned Normal disable iff in assertion causes assertion to fail Peter Monsson 12/22/2019 07:55 PM
1639 Verilator Feature Low Support $countbits (starter task) 12/15/2019 01:42 AM
1638 Verilator Feature Low Support $ferror/$fflush (starter task) 12/15/2019 01:40 AM
1637 Verilator Feature Low Support $displayb/o/h, $writeb/o/h (starter project) 12/15/2019 01:38 AM
1636 Verilator Resolved Low Add vpiTimeUnit and allow to specify time as string Stefan Wallentowitz 12/14/2019 12:28 AM
1634 Verilator Resolved Normal `uselib error with Verilator 12/13/2019 01:54 AM
1631 Verilator Resolved Normal -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with other simulators Julien Margetts 12/11/2019 10:16 PM
1628 Verilator Confirmed Normal Ongoing cleanup of SymbiFlow sv-tests (help wanted) 12/15/2019 10:41 PM
1627 Verilator Confirmed Normal Warnings and support of array concatenation 12/22/2019 07:56 PM
1626 Verilator Confirmed Normal Interface parameter circular assignment succeeds where it should not 12/22/2019 07:57 PM
1624 Verilator Confirmed Low Bad parameter width error message references parameter definition instead of reference 12/22/2019 07:57 PM
1623 Verilator Confirmed Low Interface declared in parent scope can be used incorrectly 12/22/2019 07:58 PM
1622 Verilator Confirmed Low Wrong modport directionality accross scopes doesn't trigger an error 12/22/2019 07:58 PM
1613 Verilator Confirmed Normal verilator %Warning-WIDTH false positive 12/22/2019 07:59 PM
1610 Verilog-Perl Resolved Normal Getopt thinks a path is a comment 11/21/2019 02:16 AM
1609 Verilator Feature Low Detect and warn appripriately on intentional latches Julien Margetts 12/22/2019 07:59 PM
1606 Verilator Resolved Normal Complete string methods (starter project) 12/15/2019 01:14 PM
1602 Verilator Assigned Normal Investigate Travis CMake error message Todd Strader 12/22/2019 08:00 PM
1601 Verilator Confirmed Normal Add SystemC to Travis 12/22/2019 08:00 PM
1593 Verilator Confirmed Normal Parameter-resolved constants from interface components 12/22/2019 08:01 PM
1572 Verilator Feature Normal Extend --protect-lib for foreign/embedded module use 12/22/2019 08:02 PM
1567 Verilator Feature Normal Cocotb Integration 12/22/2019 08:02 PM
1566 Verilator Confirmed Normal FST dumping is slow 10/17/2019 10:39 PM
1554 Verilator AskedReporter Normal There is a problem when Handling variables forced type conversion Todd Strader 12/22/2019 08:03 PM
1545 Verilator Confirmed Normal Warning-CASEOVERLAP is not triggering for signals wider than 12 12/22/2019 08:03 PM
1543 Verilator Feature Normal Improve performance of icache 10/06/2019 01:23 PM
1542 Verilator Feature Normal Improve performance of bit operations by vectorizing 10/06/2019 01:24 PM
1541 Verilator Feature Normal Support unpacked structs 10/06/2019 01:24 PM
1540 Verilator Feature Normal Improve internal elaboration algorithm 10/06/2019 01:00 PM
1539 Verilator Feature Normal Improve internals of inliner 10/06/2019 12:54 PM
1538 Verilator Feature Normal Support full UVM parsing and XML dump 10/06/2019 01:26 PM
1537 Verilator Feature Low Support FST structure tracing w/GTKwave 10/06/2019 12:31 PM
1524 Verilator Assigned Normal Support sensitivity to DPI function outputs Todd Strader 11/05/2019 03:09 AM
1523 Verilator Feature Normal Add waveform replay tool Todd Strader 12/18/2019 10:53 PM
1522 Verilator Feature Normal Support mutable top-level parameters for --protect-lib Todd Strader 10/25/2019 12:11 PM
1520 Verilator Feature Normal Improve --protect-lib performance Todd Strader 10/06/2019 01:30 PM
1518 Verilator Feature Normal Protect against --protect-lib Verilator runtime incompatibility Todd Strader 10/06/2019 01:27 PM
1517 Verilator Feature Normal Add support for additional simulators in --protect-lib Todd Strader 10/06/2019 01:27 PM
1516 Verilog-mode Confirmed Normal Wrong indentation after SV streaming statement 12/21/2019 03:15 PM
1515 Verilator Feature Low VPI: Log all variables that were accessed Stefan Wallentowitz 12/22/2019 08:05 PM
1514 Verilator Feature Low Switch for file to read public signals from Stefan Wallentowitz 12/22/2019 08:05 PM
1501 Verilator Confirmed Normal Support bind statements within generate blocks 12/22/2019 08:06 PM
1495 Verilog-mode Confirmed Normal Wrong statement continue alignment. 09/15/2019 03:40 PM
1489 Verilator Feature Normal Python support for Verilated designs Maarten De Braekeleer 12/22/2019 08:06 PM
1482 Verilator Feature Normal Conditional event controls ("iff") 12/22/2019 08:07 PM
1479 Verilator Feature Normal Feature Request: VerilatedVcd callback on rolloverMB Marc Jessome 12/22/2019 08:07 PM
1478 Verilator Confirmed Normal -faligned-new does not work under Travis with clang 07/18/2019 12:02 PM
1477 Verilator Assigned Normal Add macOS coverage in Travis CI 07/18/2019 10:33 AM
1470 Verilator Feature Low VPI systemtf Stefan Wallentowitz 09/26/2019 12:39 PM
1454 Verilator Feature Normal Support for loop index into generated arrays 12/22/2019 08:09 PM
1453 Verilog-mode Feature Normal AUTOLOGIC/AUTOINST for unpacked array signal input to submodule 10/18/2019 02:24 AM
1447 Verilog-mode Feature Normal Expand AUTOINST default values for parameters 05/29/2019 10:46 PM
1446 Verilog-mode Confirmed Normal SystemVerilog interface indentation in module declaration 05/29/2019 10:49 PM
1430 Verilator AskedReporter Normal Broken node on indexed interface modport Wilson Snyder 12/22/2019 08:09 PM
1404 Verilog-mode Confirmed Normal alignment within generate-if 03/03/2019 12:55 AM
1395 Verilator Feature Normal Extend UNUSED to flag signals which are not in the cone of a module output 12/22/2019 08:10 PM
1382 Verilator AskedReporter Normal Inconsistent LITENDIAN warnings on arrays 12/22/2019 08:10 PM
1373 Verilator Feature Normal Cannot write to top-level tristate ports 12/22/2019 08:11 PM
1369 Verilator Confirmed Normal Raise error / warning on continous assignment to reg Wilson Snyder 12/22/2019 08:11 PM
1366 Verilator AskedReporter Normal Large increase in design header file with threads and tracing 11/29/2018 11:13 PM
1321 Verilog-mode Confirmed Normal indentation of coverpoint is incorrect if coverpoint expression is a concatenation 12/21/2019 03:16 PM
1314 Verilator Confirmed Normal Bad scaling, if there are nasty forests of generate statements John Coiner 12/22/2019 08:12 PM
1313 Verilog-mode Confirmed Normal AUTOINST problem for module containing clocking block 07/15/2019 07:07 PM
1292 Verilator Feature Normal scr1 test suite: |-> and |=> operators are unsupported in assertions 12/22/2019 08:12 PM
1288 Verilator Confirmed Normal scr1 test suite: In some cases mixed assignment to struct member fails 12/22/2019 08:13 PM
1286 Verilator Confirmed Normal scr1 test suite: processing passes get stuck, and allocate huge amounts of system RAM when verilog contains memory blocks 03/10/2018 04:21 AM
1283 Verilog-mode Confirmed Normal Feature request: Allow user to break movement on '_' symbols 03/08/2018 02:25 PM
1278 Verilator Confirmed Normal Unsupported LHS tristate construct: ARRAYSEL 12/22/2019 08:15 PM
1272 Verilog-mode Confirmed Normal alignment and indentation issue with import and "=" for localparam 02/02/2018 12:30 AM
1257 Verilog-mode Confirmed Normal Indentation within generate construct after always block is wrong if generate/endgenerate omitted 05/10/2019 01:06 AM
1184 Verilator Feature Normal Verilator doesn't detect multiple assignment 12/22/2019 08:15 PM
1168 Verilog-mode Feature Normal Is it possible to make "begin" keyword align with case expression? 11/30/2017 06:36 AM
1167 Verilog-mode Confirmed Normal Port list is not aligned properly when the first port declaration is not start from a new line 11/19/2017 01:38 PM
1163 Verilog-mode Confirmed Normal Module mis-indent within generate statement 05/22/2017 05:42 PM
1160 Verilog-mode Confirmed Normal Understand few defconsts 05/08/2017 11:53 PM
1157 Verilog-mode Feature Normal Auto-alignment on comments in PORT declaration 04/26/2017 04:58 PM
1104 Verilator Feature Normal No support for parameterized interface in module "signal" list. 11/23/2017 05:24 PM
1096 Verilator Confirmed Normal UNOPT and UNOPTFLAT V3Split optimizations 07/12/2017 02:14 AM
1092 Verilog-mode Confirmed Normal Highlighting bug; highlights wrong block of code 11/19/2017 01:35 PM
1085 Verilog-mode Feature Normal Besides ignore regex, need force regex for auto-output 11/19/2017 01:57 PM
1082 Verilog-mode Feature Normal Smart indenting multi-line `define 08/25/2016 05:41 PM
1074 Verilog-mode Confirmed Normal Backslash inside quotes for uvm_info/error messages 11/19/2017 01:33 PM
1070 Verilog-mode Confirmed Normal Auto-completion results in runaway emacs process in emacs 24.4 on Debian using 2016-04-23-5f6855e-vpo 11/19/2017 02:00 PM
1064 Verilog-Perl Confirmed Normal Parser doesn't understand constraint implication operator ('->') 09/09/2016 08:20 AM
1048 Verilog-mode Confirmed Normal indention after 'package ... endpackage' is one level too deep 11/19/2017 01:32 PM
1047 Verilog-mode Confirmed Normal indention after 'interface class ... endclass' is one level too deep 11/19/2017 01:32 PM
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