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# Project Status Priority Subject Assignee Updated
50 Verilator Feature Normal Clock gating support? 10/28/2009 01:51 PM
63 Verilator Feature Normal False Signal unoptimizable: circular logic warning 05/27/2016 10:14 PM
225 Verilator Feature Normal hierarchical compilation of designs for scalability 03/17/2010 08:14 PM
234 Verilator Feature Normal Support time and `timescales 12/14/2019 03:16 PM
235 Verilator Feature Normal Support fork-joins and time delays 04/07/2010 01:27 PM
236 Verilator Feature Normal Support real event loop 12/21/2019 01:08 PM
286 Verilog-mode Feature Low Identation of classes inside package in SystemVerilog 11/19/2017 01:10 PM
308 Verilog-mode Feature Normal Indenting/Highlighting user defined types 02/21/2011 02:21 AM
364 Verilator Feature Normal blocking & non-blocking assigns -- verilator issues error when no logical conflict exists 11/13/2019 09:39 PM
365 Verilator Feature Normal bidrectional arrays not supported as module ports 11/23/2017 04:45 PM
366 Verilator Feature Normal Support sensitivity of arrayed variables 07/21/2011 11:31 AM
377 Verilator Feature Normal Support classes and methods 02/06/2016 11:16 PM
378 Verilator Feature Normal Support properties and assertions 03/02/2012 11:42 PM
379 Verilator Feature Normal Support dynamic memory new and delete 03/02/2012 11:42 PM
380 Verilator Feature Normal Support of VHDL93 Sebastien Van Cauwenberghe 08/10/2011 06:49 AM
386 Verilog-mode Feature Normal Indenting of user-defined data types 07/23/2019 01:05 AM
408 Verilator Confirmed Low verilator generates incorrect C++ code when genvar is used incorrectly 03/10/2012 07:09 AM
416 SVN::S4 Feature Normal s4 view command support for regexps at multiple levels of directory hierarchy Wilson Snyder 11/19/2017 01:01 PM
417 SVN::S4 Feature Normal Potential new s4 commands: doview and unview Wilson Snyder 11/19/2017 01:02 PM
418 SVN::S4 Confirmed Normal aliased entries in s4_state cause warnings on s4 update Wilson Snyder 11/19/2017 01:02 PM
419 SVN::S4 Confirmed Normal s4 update fails to remove a view when it is removed from viewspec Wilson Snyder 11/19/2017 01:02 PM
435 Verilog-mode Confirmed Normal Indenting comments on declarations in v736 11/19/2017 01:12 PM
447 Verilog-mode Confirmed Normal verilog-pretty-expr doesn't work in latest version 03/07/2012 12:23 AM
449 Verilator Confirmed Normal Using public accessor tasks/functions to read and write registers causes BLKANDNBLK error 10/18/2019 12:06 AM
468 Verilator Feature Low Support primitive instantiations 04/25/2012 12:43 AM
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