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# Project Status Priority Subject Assignee Updated
1626 Verilator Confirmed Normal Interface parameter circular assignment succeeds where it should not 12/22/2019 07:57 PM
1646 Verilator New Low $bits for dynamic/runtime usage Stefan Wallentowitz 12/22/2019 07:53 PM
1478 Verilator Confirmed Normal -faligned-new does not work under Travis with clang 07/18/2019 12:02 PM
1631 Verilator Resolved Normal -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with other simulators Julien Margetts 12/11/2019 10:16 PM
1477 Verilator Assigned Normal Add macOS coverage in Travis CI 07/18/2019 10:33 AM
1517 Verilator Feature Normal Add support for additional simulators in --protect-lib Todd Strader 10/06/2019 01:27 PM
1601 Verilator Confirmed Normal Add SystemC to Travis 12/22/2019 08:00 PM
1636 Verilator Resolved Low Add vpiTimeUnit and allow to specify time as string Stefan Wallentowitz 12/14/2019 12:28 AM
1523 Verilator Feature Normal Add waveform replay tool Todd Strader 12/18/2019 10:53 PM
418 SVN::S4 Confirmed Normal aliased entries in s4_state cause warnings on s4 update Wilson Snyder 11/19/2017 01:02 PM
1272 Verilog-mode Confirmed Normal alignment and indentation issue with import and "=" for localparam 02/02/2018 12:30 AM
1404 Verilog-mode Confirmed Normal alignment within generate-if 03/03/2019 12:55 AM
1157 Verilog-mode Feature Normal Auto-alignment on comments in PORT declaration 04/26/2017 04:58 PM
892 Verilog-mode Feature Normal Auto-assignment via pattern matching 11/19/2017 01:58 PM
1070 Verilog-mode Confirmed Normal Auto-completion results in runaway emacs process in emacs 24.4 on Debian using 2016-04-23-5f6855e-vpo 11/19/2017 02:00 PM
962 Verilog-mode Confirmed Normal AUTOARG order with AUTOINPUT 09/04/2015 01:05 PM
1313 Verilog-mode Confirmed Normal AUTOINST problem for module containing clocking block 07/15/2019 07:07 PM
1453 Verilog-mode Feature Normal AUTOLOGIC/AUTOINST for unpacked array signal input to submodule 10/18/2019 02:24 AM
1019 Verilog-mode Confirmed Normal AUTOOUTPUTEVERY and AUTOWIRE: Signal declared multiple times 11/19/2017 01:31 PM
1074 Verilog-mode Confirmed Normal Backslash inside quotes for uvm_info/error messages 11/19/2017 01:33 PM
1624 Verilator Confirmed Low Bad parameter width error message references parameter definition instead of reference 12/22/2019 07:57 PM
1314 Verilator Confirmed Normal Bad scaling, if there are nasty forests of generate statements John Coiner 12/22/2019 08:12 PM
1085 Verilog-mode Feature Normal Besides ignore regex, need force regex for auto-output 11/19/2017 01:57 PM
365 Verilator Feature Normal bidrectional arrays not supported as module ports 11/23/2017 04:45 PM
364 Verilator Feature Normal blocking & non-blocking assigns -- verilator issues error when no logical conflict exists 11/13/2019 09:39 PM
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