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# Project Status Priority Subject Assignee Updated
1664 Verilator New Normal Verilator Generates C++ code which does not compile ... 04/27/2020 01:04 PM
1663 Verilator New Normal Verilator Generates C++ code which does not compile ... 04/27/2020 07:31 AM
1659 Verilog-Perl Resolved Normal Preprocessor doesn't handle one case of definition substitution properly Wilson Snyder 01/11/2020 02:16 PM
1184 Verilator Feature Normal Verilator doesn't detect multiple assignment 12/22/2019 08:15 PM
1278 Verilator Confirmed Normal Unsupported LHS tristate construct: ARRAYSEL 12/22/2019 08:15 PM
1288 Verilator Confirmed Normal scr1 test suite: In some cases mixed assignment to struct member fails 12/22/2019 08:13 PM
1292 Verilator Feature Normal scr1 test suite: |-> and |=> operators are unsupported in assertions 12/22/2019 08:12 PM
1314 Verilator Confirmed Normal Bad scaling, if there are nasty forests of generate statements John Coiner 12/22/2019 08:12 PM
1369 Verilator Confirmed Normal Raise error / warning on continous assignment to reg Wilson Snyder 12/22/2019 08:11 PM
1373 Verilator Feature Normal Cannot write to top-level tristate ports 12/22/2019 08:11 PM
1382 Verilator AskedReporter Normal Inconsistent LITENDIAN warnings on arrays 12/22/2019 08:10 PM
1395 Verilator Feature Normal Extend UNUSED to flag signals which are not in the cone of a module output 12/22/2019 08:10 PM
1430 Verilator AskedReporter Normal Broken node on indexed interface modport Wilson Snyder 12/22/2019 08:09 PM
1454 Verilator Feature Normal Support for loop index into generated arrays 12/22/2019 08:09 PM
1479 Verilator Feature Normal Feature Request: VerilatedVcd callback on rolloverMB Marc Jessome 12/22/2019 08:07 PM
1482 Verilator Feature Normal Conditional event controls ("iff") 12/22/2019 08:07 PM
1489 Verilator Feature Normal Python support for Verilated designs Maarten De Braekeleer 12/22/2019 08:06 PM
1501 Verilator Confirmed Normal Support bind statements within generate blocks 12/22/2019 08:06 PM
1514 Verilator Feature Low Switch for file to read public signals from Stefan Wallentowitz 12/22/2019 08:05 PM
1515 Verilator Feature Low VPI: Log all variables that were accessed Stefan Wallentowitz 12/22/2019 08:05 PM
1545 Verilator Confirmed Normal Warning-CASEOVERLAP is not triggering for signals wider than 12 12/22/2019 08:03 PM
1554 Verilator AskedReporter Normal There is a problem when Handling variables forced type conversion Todd Strader 12/22/2019 08:03 PM
1567 Verilator Feature Normal Cocotb Integration 12/22/2019 08:02 PM
1572 Verilator Feature Normal Extend --protect-lib for foreign/embedded module use 12/22/2019 08:02 PM
1593 Verilator Confirmed Normal Parameter-resolved constants from interface components 12/22/2019 08:01 PM
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