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Issue #1467

Updated by Wilson Snyder 6 months ago

Trying to debug the root cause of multiple errors. Here is a minimal example I've managed to extract:

<pre><code class="delphi">
module dut #(
parameter DEPTH = 16,
parameter WIDTH = 32,
parameter RAM_SPLIT_WIDTH = 16
)
(
output logic [WIDTH-1:0] ram_dataout
);

localparam RAM_ADDR_WIDTH = $clog2(DEPTH);
localparam NUM_RAM_BLOCKS = WIDTH/RAM_SPLIT_WIDTH + (WIDTH%RAM_SPLIT_WIDTH > 0);
typedef logic [NUM_RAM_BLOCKS:0][31:0] block_index_t;

function automatic block_index_t index_calc(input int WIDTH, NUM_RAM_BLOCKS);
index_calc[0] = '0;
for(int i = 0; i < NUM_RAM_BLOCKS; i++) index_calc[i+1] = WIDTH/NUM_RAM_BLOCKS + (i < (WIDTH%NUM_RAM_BLOCKS));
for(int i = 0; i < NUM_RAM_BLOCKS; i++) index_calc[i+1] = index_calc[i+1] + index_calc[i];
return index_calc;
endfunction

localparam block_index_t RAM_BLOCK_INDEX = index_calc(WIDTH, NUM_RAM_BLOCKS);

generate
begin : ram_dataout_gen
for (genvar i = 0; i < NUM_RAM_BLOCKS; i++) begin
always_comb ram_dataout[RAM_BLOCK_INDEX[i+1]-1:RAM_BLOCK_INDEX[i]] = 0;
end
end
endgenerate

endmodule

module top (
input clk,
output logic [31:0] ram_dataout
);

dut dut0(.*);

endmodule
</code></pre>

<pre>
%Warning-WIDTH: top.sv:11: Operator ADD expects 32 or 6 bits on the RHS, but RHS's GTS generates 1 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: top.sv:16: Operator ADD expects 32 bits on the RHS, but RHS's LTS generates 1 bits.
%Error: top.sv:26: [-1:0] Range extract has backward bit ordering, perhaps you wanted [0:-1]
</pre>



So Verilator incorrectly evaluates RAM_BLOCK_INDEX[1] to 0.
Works fine in VCS/DC.

verilator --lint-only -sv -top-module top top.sv

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