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News

Verilator: Verilator 3.914 Released

Added by Wilson Snyder 4 days ago

Verilator 3.914 2017-10-14

  • Added new examples/ directory with appropriate examples. This replaces the old test_c and test_sc directories.
  • Add --getenv option for simplifying Makefiles.
  • Add --x-initial option for specifying initial value assignment behavior.
  • Add --no-relative-cfuncs and related default optimization, bug1224. [John Coiner]
  • Add /*verilator tag*/ for XML extraction applications. [Chris Randall]
  • The internal test_verilated test directory is moved to be part of test_regress.
  • The experimental VL_THREADED setting (only, not normal mode) now requires C++11.
  • Fix over-aggressive inlining, bug1223. [John Coiner]
  • Fix Ubuntu 17.10 issues, bug1223 partial. [John Coiner]
  • Fix compiler warning when WIDTH warning ignored on large compare.
  • Fix memory leak in VerilatedVcd dumps, bug1222 partial. [Shareef Jalloq]
  • Fix unnecessary Vdly variables, bug1224 partial. [John Coiner]
  • Fix conditional slices and add related optimizations.
  • Fix `` expansion of `defines, bug1225, bug1227, bug1228. [Odd Magne Reitan]
  • Fix -E duplicating output, bug1226. [Odd Magne Reitan]
  • Fix float-conversion warning, bug1229. [Robert Henry]

Verilator: Verilator 3.912 Released

Added by Wilson Snyder 25 days ago

Verilator 3.912 2017-09-23

  • Verilated headers no longer "use namespace std;" User's code without "std::" prefixes may need "use namespace std;" to compile.
  • Support or/and/xor array intrinsic methods, bug1210. [Mike Popoloski]
  • Support package export, bug1217. [Usuario Eda]
  • Fix ordering of arrayed cell wide connections, bug1202 partial. [Mike Popoloski]
  • Support module port parameters without defaults, bug 1213. [Mike Popoloski]
  • Add performance information to --stats file.
  • Simplify VL_CONST_W macro generation for faster compiles.
  • Fix LITENDIAN warning on arrayed cells, bug1202. [Mike Popoloski]
  • Fix enum ranges without colons, bug1204. [Mike Popoloski]
  • Fix GCC noreturn compile error, bug1209. [Mike Popoloski]
  • Fix constant function default parameters, bug1211. [Mike Popoloski]
  • Fix non-colon array of interface modports, bug1212. [Mike Popoloski]
  • Fix .name connections on interfaces, bug1214. [Mike Popoloski]
  • Fix wide array indices causing compile error.
  • Better optimize Shift-And, and replication constructs.

Verilog-Perl: Verilog-Perl 3.440 Released

Added by Wilson Snyder about 2 months ago

Verilog::Language 3.440 2017-08-31

  • Support for buses and concats in Netlist, msg1626. [by Stefan Tauner]
  • Support pragma protect begin_protected/end_protected, msg2313. [George Cuan]

Verilator: Verilator 3.908 Released

Added by Wilson Snyder about 2 months ago

Verilator 3.908 2017-08-28

  • Support x in $readmem, bug1180. [Arthur Kahlich]
  • Support packed struct DPI imports, bug1190. [Rob Stoddard]
  • Fix GCC 6 warnings.
  • Fix compile error on unused VL_VALUEPLUSARGS_IW, bug1181. [Thomas J Whatson]
  • Fix undefined VL_POW_WWI. [Clifford Wolf]
  • Fix internal error on unconnected inouts, bug1187. [Rob Stoddard]

Verilator: Verilator 3.906 Released

Added by Wilson Snyder 4 months ago

  • Verilator 3.906 2017-06-22
  • Support set_time_unit/set_time_precision in C traces, msg2261.
  • Fix extract of packed array with non-zero LSB, bug1172. [James Pallister]
  • Fix shifts by more than 32-bit numbers, bug1174. [Clifford Wolf]
  • Fix power operator on wide constants, bug761. [Clifford Wolf]
  • Fix .* on interface pins, bug1176. [Maciej Piechotka]
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