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Verilator 3.662 Released

Added by Wilson Snyder almost 12 years ago

Verilator 3.662 2008/04/25

  • Add Verilog 2005 $clog2() function. This is useful in calculating bus-widths from parameters.
  • Support /**/ comments in -f option files. [Stefan Thiede]
  • Add error message when modules have duplicate names. [Stefan Thiede]
  • Support defines terminated in EOF, though against spec. [Stefan Thiede]
  • Support optional argument to $finish and $stop. [by Stefan Thiede]
  • Support ranges on gate primitive instantiations. [Stefan Thiede]
  • Ignore old standard(ish) Verilog-XL defines. [by Stefan Thiede]
  • Fix "always @ ((a) or (b))" syntax error. [by Niranjan Prabhu]
  • Fix "output reg name=expr;" syntax error. [Martin Scharrer]
  • Fix multiple .v files being read in random order. [Stefan Thiede]
  • Fix internal error when params get non-constants. [Johan Wouters]
  • Fix bug introduced in 3.661 with parametrized defines.

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