Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  IPC::Locker
  Parallel::Forker
  Voneline
General Info
  Papers

Verilator 3.661 Released

Added by Wilson Snyder about 12 years ago

Verilator 3.661 2008/04/04

  • The --enable-defenv configure option added in 3.660 is now the default. This hard-codes a default for VERILATOR_ROOT etc in the executables.
  • Add --language option for supporting older code. [Stefan Thiede]
  • Add --top-module option to select between multiple tops. [Stefan Thiede]
  • Unsized concatenates now give WIDTHCONCAT warnings. [Jonathan Kimmitt] Previously they threw fatal errors, which in most cases is correct according to spec, but can be incorrect in presence of parameter values.
  • Support functions with "input integer". [Johan Wouters]
  • Ignore delays attached to gate UDPs. [Stefan Thiede]
  • Fix SystemVerilog parameterized defines with `` expansion, and fix extra whitespace inserted on substitution. [Vladimir Matveyenko]
  • Fix no-module include files on command line. [Stefan Thiede]
  • Fix dropping of backslash quoted-quote at end of $display.
  • Fix task output pin connected to non-variables. [Jonathan Kimmitt]
  • Fix missing test_v in install datadir. [Holger Waechtler]
  • Fix internal error after MSB < LSB error reported to user. [Stefan Thiede]

Comments