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News

Verilator: Verilator 4.008 Released

Added by Wilson Snyder 7 months ago

  • Verilator 4.008 2018-12-01
  • Support "ref" and "const ref" pins and functions, bug1360. [Jake Longo]
  • In --xml-only show the original unmodified names, and add module_files and cells similar to Verilog-Perl, msg2719. [Kanad Kanhere]
  • Add CONTASSREG error on continuous assignments to regs, bug1369. [Peter Gerst]
  • Add PROCASSWIRE error on behavioral assignments to wires, msg2737. [Neil Turton]
  • Add IMPORTSTAR warning on import::* inside $unit scope.
  • Fix --trace-lxt2 compile error on MinGW, msg2711. [HyungKi Jeong]
  • Fix hang on bad pattern keys, bug1364. [Matt Myers]
  • Fix crash due to cygwin bug in getline, bug1349. [Affe Mao]
  • Fix __Slow files getting compiled with OPT_FAST, bug1370. [Thomas Watts]

Verilator: RISC-V Contest Chooses Verilator

Added by Wilson Snyder 7 months ago

The 2018 RISC-V design contest has announced all submissions must be submitted only using Verilator.

The contest is to design a RISC-V soft CPU core, run by the RISC-V Foundation, and is sponsored by Google, Antmicro, Lattice Semiconductor and Microsemi. For more details see https://riscv.org/2018contest/

Verilator: Verilator 4.006 Released

Added by Wilson Snyder 8 months ago

Verilator 4.006 2018-10-27

  • Add --pp-comments, msg2700. [Robert Henry]
  • Add --dump-defines.
  • For --trace-fst, save enum decoding information, bug1358. [Sergi Granell] (To visualize enumeration data you must use GTKwave 3.3.95 or newer.)
  • For --trace-fst, instead of *.fst.hier, put data into *.fst. [Tony Bybell]
  • Fix --trace-lxt2 compile error on MinGW, msg2667. [HyungKi Jeong]
  • Fix Windows .exe not found, bug1361. [Patrick Stewart]

Verilator: Verilator 4.004 Released

Added by Wilson Snyder 9 months ago

Verilator 4.004 2018-10-6

  • Add GTKWave FST native tracing, bug1356. [Sergi Granell] (Verilator developers need to pull the latest vcddiff.)
  • Support $past. [Dan Gisselquist]
  • Support restrict, bug1350. [Clifford Wolf]
  • Rename include/lxt2 to include/gtkwave.
  • Fix replication of 64-bit signal change detects.
  • Fix Mac OSX 10.13.6 / LLVM 9.1 compile issues, bug1348. [Kevin Kiningham]
  • Fix MinGW compile issues, msg2636. [HyungKi Jeong]

Verilator: Verilator 4.002 Released

Added by Wilson Snyder 9 months ago

Verilator 4.002 2018-09-16

This is a major release. Any patches may require major rework to apply. [Thanks everyone]

  • Add multithreaded model generation.
  • Add runtime arguments.
  • Add GTKWave LXT2 native tracing, bug1333. [Yu Sheng Lin]
  • Note $random has new algorithm; results may vary vs. previous versions.
  • Better optimize large always block splitting, bug1244. [John Coiner]
  • Add new reloop optimization for repetitive assignment compression.
  • Support string.atoi and similar methods, bug1289. [Joel Holdsworth]
  • Fix internals to be C++ null-pointer-check clean.
  • Fix internals to avoid 'using namespace std'.
  • Fix Verilation performance issues, bug1316. [John Coiner]
  • Fix clocker attributes to not propagate on concats. [John Coiner]
  • Fix first clock edge and --x-initial-edge, bug1327. [Rupert Swarbrick]
  • Fix compile error on tracing of string arrays, bug1338. [Iztok Jeras]
  • Fix number parsing with newline after radix, bug1340. [George Cuan]
  • Fix string ?: conditional type resolution, bug1345. [Iztok Jeras]
  • Fix duplicate symbol error on generate tri, bug1347. [Tomas Dzetkulic]

Verilator: Verilator 4.000 approaches; announcement at OrCONF

Added by Wilson Snyder 10 months ago

We're glad to announce that Verilator 4.000 is now in beta test and will be formally announced at OrConf 2018

The git tree now contains the beta, please give it a try, and enjoy the main new feature of multithreaded simulation!

  • If your git repo was using the 'master' branch (the default) as upstream you need do nothing, you'll now get the 4.000 sources.
  • If you were using the git 'develop-v4' branch, that branch is now merged into 'master'. 'develop-v4' was deleted. Pulling from a branch that has 'develop-v4' as upstream may give a "Your branch is based on 'origin/develop-v4', but the upstream is gone" or "Your configuration specifies to merge with the ref 'refs/heads/develop-v4' from the remote, but no such ref was fetched" error. You need to do this:

    git branch --set-upstream-to=origin/master

  • A new 'v3/devel' branch was made pointing to the previous origin/master (with Version 3.xxx) and will only be developed further if another 3.xxx release is required due to a serious issue.

Verilator: Verilator 3.926 Released

Added by Wilson Snyder 10 months ago

Verilator 3.926 2018-08-22

  • Add OBJCACHE envvar support to examples and generated Makefiles.
  • Change MODDUP errors to warnings, msg2588. [Marshal Qiao]
  • Fix define argument stringification (`"), broke since 3.914. [Joe DErrico]
  • Fix to ignore Unicode UTF-8 BOM sequences, msg2576. [HyungKi Jeong]
  • Fix function inlining inside certain while loops, bug1330. [Julien Margetts]

Verilog-Perl: Verilog-Perl 3.454 Released

Added by Wilson Snyder 10 months ago

Verilog::Language 3.454 2018-08-21

  • Support parsing around Cadence protected meta-comments.
  • Fix define argument stringification (`"), broke since 3.446. [Joe DErrico]
  • Fix to ignore Unicode UTF-8 BOM sequences, msg2576. [HyungKi Jeong]
(11-20/254)

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