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Verilog-Perl: Verilog-Perl 3.440 Released

Added by Wilson Snyder 7 months ago

Verilog::Language 3.440 2017-08-31

  • Support for buses and concats in Netlist, msg1626. [by Stefan Tauner]
  • Support pragma protect begin_protected/end_protected, msg2313. [George Cuan]

Verilator: Verilator 3.908 Released

Added by Wilson Snyder 7 months ago

Verilator 3.908 2017-08-28

  • Support x in $readmem, bug1180. [Arthur Kahlich]
  • Support packed struct DPI imports, bug1190. [Rob Stoddard]
  • Fix GCC 6 warnings.
  • Fix compile error on unused VL_VALUEPLUSARGS_IW, bug1181. [Thomas J Whatson]
  • Fix undefined VL_POW_WWI. [Clifford Wolf]
  • Fix internal error on unconnected inouts, bug1187. [Rob Stoddard]

Verilator: Verilator 3.906 Released

Added by Wilson Snyder 9 months ago

  • Verilator 3.906 2017-06-22
  • Support set_time_unit/set_time_precision in C traces, msg2261.
  • Fix extract of packed array with non-zero LSB, bug1172. [James Pallister]
  • Fix shifts by more than 32-bit numbers, bug1174. [Clifford Wolf]
  • Fix power operator on wide constants, bug761. [Clifford Wolf]
  • Fix .* on interface pins, bug1176. [Maciej Piechotka]

Verilator: Verilator 3.904 Released

Added by Wilson Snyder 10 months ago

Verilator 3.904 2017-05-30

  • Fix non-cutable ordering loops on clock arrays, bug1009. [Todd Strader]
  • Support ports of array of reals, bug1154. [J Briquet]
  • Support arrayed parameter overrides, bug1153. [John Stevenson]
  • Support $value$plusargs with variables, bug1165. [Wesley Terpstra]
  • Support modport access to un-modport objects, bug1161. [Todd Strader]
  • Add stack trace when can't optimize function, bug1158. [Todd Strader]
  • Add warning on mis-sized literal, bug1156. [Todd Strader]
  • Fix interface functions returning wrong parameters, bug996. [Todd Strader]
  • Fix non-arrayed cells with interface arrays, bug1153. [John Stevenson]
  • Fix --assert with complex case statements, bug1164. [Enzo Chi]

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