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News

Schedule::Load: Schedule::Load 3.060 is Released

Added by Wilson Snyder over 9 years ago

Schedule::Load 3.060 2008/12/08

  • Quickly service requests when a reporter is responding very slowly.
  • Add to "rschedule status" the most recent slchoosed syslog messages.
  • Add to "rschedule status" the slreporting hostname.
  • Fix rschedule sort warnings when reporter is going up and down.

Verilator: Verilator 3.681 Released

Added by Wilson Snyder over 9 years ago

Verilator 3.681 2008/11/12

  • Add SystemVerilog unique and priority case.
  • Include Verilog file's directory name in coverage reports.
  • Fix 'for' under 'generate-for' causing error; bug38. [Rafael Shirakawa]
  • Fix coverage hierarchy being backwards with inlining. [Vasu Arasanipalai]
  • Fix GCC 4.3 compile error; bug35. [Lane Brooks]
  • Fix MSVC compile error; bug42. [John Stroebel]

Verilog-Perl: Verilog-Perl 3.044 Released

Added by Wilson Snyder over 9 years ago

Verilog::Language 3.044 2008/11/10

  • Support SystemVerilog unique and priority case, bug33. [by Nicky Ayoub]
  • Support SystemVerilog timeunit and timeprecision, bug34. [by Nicky Ayoub]
  • Support SystemVerilog package items, bug39. [by Nick Ayoub]
  • Expand environment variables in Verilog::Getopt. [Lawrence Butcher]
  • Fix Verilog::EditModules when modules wrapped in ifdef. [Mat Zeno]

Veripool: Veripool on new hardware

Added by Wilson Snyder over 9 years ago

Today the Veripool server was moved to faster hardware in order to decrease latency at peak periods. The site software was also been updated to the most recent version of Redmine. As always, please contact us if you see any problems.

Verilator: Verilator 3.680 Released

Added by Wilson Snyder over 9 years ago

Verilator 3.680 2008/10/08

  • Support negative bit indexes. [Stephane Laurent] Tracing negative indexes requires latest Verilog-Perl and SystemPerl.
  • Suppress width warnings between constant strings and wider vectors. [Rodney Sinclair]
  • Expand environment variables in -f input files. [Lawrence Butcher]
  • Report error if port declaration is missing; bug32. [Guy-Armand Kamendje]
  • Fix genvars causing link error when using --public. [Chris Candler]

SystemPerl: SystemPerl 1.300 Released

Added by Wilson Snyder over 9 years ago

SystemPerl 1.300 2008/10/01

  • Many improvements to coverage, including coverage groups and automatic binning - see the documentation for details. [by Robert Woods-Corwin]
  • The SP_COVERAGE define must now be set when doing coverage. This accelerates compilation and run-time when not using coverage.
  • Coverage across multiple hierarchies is now compressed together, as per the SystemVerilog standard. Use SP_COVER_INSERT(..., per_instance,1) to override this behavior.
  • Added "#sp slow" directive for splitting up large files into portions that can be compiled with less aggressive optimization.
  • Support more arguments to SP_COVER_INSERT. [by Robert Woods-Corwin]
  • Fix string.h compile error. [Rodney Sinclair]
  • Fix tracing signals with negative lsbs. [Stephane Laurent]
  • Fix cpan-testers mis-reporting FAIL when no flex installed.

Verilog-Perl: Verilog-Perl 3.043 Released

Added by Wilson Snyder over 9 years ago

Verilog::Language 3.043 2008/09/28

  • Ignore Verilog-XL defines (suppress_faults, etc). [Nicky Ayoub]
  • Fix cpan-testers mis-reporting FAIL when no flex installed.
  • Fix Perl Critic error when not installed, rt39654. [Andreas Koening]

Verilator: Verilator 3.671 Released

Added by Wilson Snyder over 9 years ago

Verilator 3.671 2008/09/19

  • SystemC uint64_t pins are now the default instead of sc_bv<64>. Use --no-pins64 for backward compatibility.
  • Support SystemVerilog "cover property" statements.
  • When warnings are disabled on signals that are flattened out, disable the warnings on the signal(s) that replace it.
  • Add by-design and by-module subtotals to verilator_profcfunc.
  • Fix extra evaluation of pure combo blocks in SystemC output.
  • Add IMPERFECTSCH warning, disabled by default.
  • Support coverage under SystemPerl 1.285 and newer.
  • Fix stack overflow on large ? : trees. [John Sanguinetti]
  • Support arbitrary characters in identifiers. [Stephane Laurent]

Verilog-Perl: Verilog-Perl 3.042 Released

Added by Wilson Snyder over 9 years ago

Verilog::Language 3.042 2008/09/19

  • Add Netlist net, port and module ->delete methods. [Daniel Schoch]
  • Add Netlist modules_sorted_level and ->level method. [Daniel Schoch]
  • Add vpm $uerror_clk and $uwarn_clk assertions.
  • Add vpm $ucover_clk coverage expansions.
  • Vpm now enables `line comments unless using Verilog 1995.
  • Fix verilog_text to output wire values. [by Jeff Short]
  • Fix parsing signals with negative lsbs. [Stephane Laurent]
(201-210/233)

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