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News

Veripool: Veripool on new hardware

Added by Wilson Snyder over 11 years ago

Today the Veripool server was moved to faster hardware in order to decrease latency at peak periods. The site software was also been updated to the most recent version of Redmine. As always, please contact us if you see any problems.

Verilator: Verilator 3.680 Released

Added by Wilson Snyder over 11 years ago

Verilator 3.680 2008/10/08

  • Support negative bit indexes. [Stephane Laurent] Tracing negative indexes requires latest Verilog-Perl and SystemPerl.
  • Suppress width warnings between constant strings and wider vectors. [Rodney Sinclair]
  • Expand environment variables in -f input files. [Lawrence Butcher]
  • Report error if port declaration is missing; bug32. [Guy-Armand Kamendje]
  • Fix genvars causing link error when using --public. [Chris Candler]

SystemPerl: SystemPerl 1.300 Released

Added by Wilson Snyder over 11 years ago

SystemPerl 1.300 2008/10/01

  • Many improvements to coverage, including coverage groups and automatic binning - see the documentation for details. [by Robert Woods-Corwin]
  • The SP_COVERAGE define must now be set when doing coverage. This accelerates compilation and run-time when not using coverage.
  • Coverage across multiple hierarchies is now compressed together, as per the SystemVerilog standard. Use SP_COVER_INSERT(..., per_instance,1) to override this behavior.
  • Added "#sp slow" directive for splitting up large files into portions that can be compiled with less aggressive optimization.
  • Support more arguments to SP_COVER_INSERT. [by Robert Woods-Corwin]
  • Fix string.h compile error. [Rodney Sinclair]
  • Fix tracing signals with negative lsbs. [Stephane Laurent]
  • Fix cpan-testers mis-reporting FAIL when no flex installed.

Verilog-Perl: Verilog-Perl 3.043 Released

Added by Wilson Snyder over 11 years ago

Verilog::Language 3.043 2008/09/28

  • Ignore Verilog-XL defines (suppress_faults, etc). [Nicky Ayoub]
  • Fix cpan-testers mis-reporting FAIL when no flex installed.
  • Fix Perl Critic error when not installed, rt39654. [Andreas Koening]

Verilator: Verilator 3.671 Released

Added by Wilson Snyder over 11 years ago

Verilator 3.671 2008/09/19

  • SystemC uint64_t pins are now the default instead of sc_bv<64>. Use --no-pins64 for backward compatibility.
  • Support SystemVerilog "cover property" statements.
  • When warnings are disabled on signals that are flattened out, disable the warnings on the signal(s) that replace it.
  • Add by-design and by-module subtotals to verilator_profcfunc.
  • Fix extra evaluation of pure combo blocks in SystemC output.
  • Add IMPERFECTSCH warning, disabled by default.
  • Support coverage under SystemPerl 1.285 and newer.
  • Fix stack overflow on large ? : trees. [John Sanguinetti]
  • Support arbitrary characters in identifiers. [Stephane Laurent]

Verilog-Perl: Verilog-Perl 3.042 Released

Added by Wilson Snyder over 11 years ago

Verilog::Language 3.042 2008/09/19

  • Add Netlist net, port and module ->delete methods. [Daniel Schoch]
  • Add Netlist modules_sorted_level and ->level method. [Daniel Schoch]
  • Add vpm $uerror_clk and $uwarn_clk assertions.
  • Add vpm $ucover_clk coverage expansions.
  • Vpm now enables `line comments unless using Verilog 1995.
  • Fix verilog_text to output wire values. [by Jeff Short]
  • Fix parsing signals with negative lsbs. [Stephane Laurent]

Vregs: Vregs 1.460 Released

Added by Wilson Snyder over 11 years ago

Vregs 1.460 2008/09/15

  • Vreg now does not create files by default. Use --files to get all files, or specific flags to enable each output.
  • VregsRegEntry now includes register attribute string.
  • With -nofielddefines attribute, suppress class and field definitions. This avoids the almost duplicate defines for derived registers.
  • With -packholes attribute, reduce VregsRegInfo memory usage on registers with large spacing between entries. [Brian Cassell]
  • Allow package attributes to set values.
  • Fix CM# defines with registers over 32 bits. [Vasu Arasanipalai]
  • Fix Perl warning when registers have no bits. [by Vasu Arasanipalai]

Verilog-Perl: Verilog-Perl 3.041 Released

Added by Wilson Snyder over 11 years ago

Verilog::Language 3.041 2008/09/03

  • Netlist errors are now always reported through the new Verilog::Netlist::Logger class. This allows errors to be caught or specially handled. [Miguel Corazao, AMD]

Verilog-Perl: Verilog::Language 3.040 Released

Added by Wilson Snyder over 11 years ago

Verilog::Language 3.040 2008/08/20

  • Add Netlist::Net->value containing parameter values. [Ron D Smith]
  • Added Verilog::Netlist/Verilog::Parser preproc option. [by Miguel Corazao, AMD]
  • Support =, =, etc, and +, - operators. [Sean de la Haye]
  • Support "cover property."
  • Eliminated automatic error printing upon application termination. [by Miguel Corazao, AMD]
  • Fix syntax error when "`include `defname" is ifdefed. [John Dickol]
  • Fix error when macro call has commas in concatenate. [John Dickol]
  • Fix compile errors under Fedora 9, GCC 4.3.0. [by Jeremy Bennett]
(231-240/259)

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