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News

Verilog-Perl: Verilog::Language 3.040 Released

Added by Wilson Snyder over 11 years ago

Verilog::Language 3.040 2008/08/20

  • Add Netlist::Net->value containing parameter values. [Ron D Smith]
  • Added Verilog::Netlist/Verilog::Parser preproc option. [by Miguel Corazao, AMD]
  • Support =, =, etc, and +, - operators. [Sean de la Haye]
  • Support "cover property."
  • Eliminated automatic error printing upon application termination. [by Miguel Corazao, AMD]
  • Fix syntax error when "`include `defname" is ifdefed. [John Dickol]
  • Fix error when macro call has commas in concatenate. [John Dickol]
  • Fix compile errors under Fedora 9, GCC 4.3.0. [by Jeremy Bennett]

SystemPerl: SystemPerl 1.283 Released

Added by Wilson Snyder over 11 years ago

SystemPerl 1.283 2008/8/14

  • Support SystemC 2.2.0 20070314 without warnings.
  • Report tracer write problems as fatal errors. [Ed Spittles]
  • Fix systemc-mode.el to support GNU Emacs 22.

Verilator: Verilator 3.670 Released

Added by Wilson Snyder over 11 years ago

Verilator 3.670 2008/07/23

  • Add --x-assign=fast option, and make it the default. This chooses performance over reset debugging. See the manual.
  • Add --autoflush, for flushing streams after $display. [Steve Tong]
  • Add CASEZWITHX lint warning and if disabled fix handling of casez with Xs.
  • Add $feof, $fgetc, $fgets, $fflush, $fscanf, $sscanf. [Holger Waechtler]
  • Add $stime. [Holger Waechtler]
  • Add $random.
  • Add --Wfuture-, for improving forward compatibility.
  • Fix verilator_includer not being installed properly. [Holger Waechtler]
  • Fix IMPURE errors due to X-assignment temporary variables. [Steve Tong]
  • Fix "lvalue" errors with public functions; bug25. [CY Wang]
  • Add WIDTH warning to $fopen etc file descriptors.
  • Internal changes to how $displays get compiled and executed.

Verilator: Verilator 3.665 Released

Added by Wilson Snyder almost 12 years ago

Verilator 3.665 2008/06/25

  • Ignore "// verilator" comments alone on endif lines. [Rodney Sinclair]
  • "Make install" now installs verilator_includer and verilator_profcfunc.
  • Fix tracing missing changes on undriven public wires. [Rodney Sinclair]
  • Fix syntax error when "`include `defname" is ifdefed. [John Dickol]
  • Fix error when macro call has commas in concatenate. [John Dickol]
  • Fix compile errors under Fedora 9, GCC 4.3.0. [by Jeremy Bennett]
  • Fix Makefile to find headers/libraries under prefix. [by Holger_Waechtler]

Verilator: Verilator GIT Access

Added by Wilson Snyder almost 12 years ago

Anonymous git access has been added to the Verilator source repository. This allows retrieval to the current un-released development code, in addition to all recent released versions.

For more details, see http://www.veripool.org/projects/verilator/wiki/Installing

Verilog-Perl: Verilog-Perl 3.025 Released

Added by Wilson Snyder almost 12 years ago

Verilog::Language 3.025 2008/05/07

  • Fix "output reg name=expr;" bug34649 syntax error. [Martin Scharrer]
  • Fix functions with "input integer". [Johan Wouters]
  • Fix bug introduced in 3.024 with parametrized defines.
  • Fix compiler warnings under GCC 4.2.1.
  • Fix "endclass" keyword misspelling. [John Dickol]
  • Fix preprocessor `else after series of `elsif. [Mark Nodine]
  • Fix parametrized defines calling define with comma. [Joshua Wise]

Verilator: Verilator 3.663 Released

Added by Wilson Snyder almost 12 years ago

Verilator 3.663 2008/05/07

  • Add DESTDIR to Makefiles to assist RPM construction. [Gunter Dannoritzer]
  • Fix compiler warnings under GCC 4.2.1.
  • Fix preprocessor `else after series of `elsif. [Mark Nodine]
  • Fix parametrized defines calling define with comma. [Joshua Wise]
  • Fix comma separated list of primitives. [by Bryan Brady]

Verilator: Verilator 3.662 Released

Added by Wilson Snyder almost 12 years ago

Verilator 3.662 2008/04/25

  • Add Verilog 2005 $clog2() function. This is useful in calculating bus-widths from parameters.
  • Support /**/ comments in -f option files. [Stefan Thiede]
  • Add error message when modules have duplicate names. [Stefan Thiede]
  • Support defines terminated in EOF, though against spec. [Stefan Thiede]
  • Support optional argument to $finish and $stop. [by Stefan Thiede]
  • Support ranges on gate primitive instantiations. [Stefan Thiede]
  • Ignore old standard(ish) Verilog-XL defines. [by Stefan Thiede]
  • Fix "always @ ((a) or (b))" syntax error. [by Niranjan Prabhu]
  • Fix "output reg name=expr;" syntax error. [Martin Scharrer]
  • Fix multiple .v files being read in random order. [Stefan Thiede]
  • Fix internal error when params get non-constants. [Johan Wouters]
  • Fix bug introduced in 3.661 with parametrized defines.
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