Verilog::Language 3.456 2018-10-28
- Fix number parsing with newline after radix, bug1340. [George Cuan]
Verilator 4.006 2018-10-27
- Add --pp-comments, msg2700. [Robert Henry]
- For --trace-fst, save enum decoding information, bug1358. [Sergi Granell]
(To visualize enumeration data you must use GTKwave 3.3.95 or newer.)
- For --trace-fst, instead of *.fst.hier, put data into *.fst. [Tony Bybell]
- Fix --trace-lxt2 compile error on MinGW, msg2667. [HyungKi Jeong]
- Fix Windows .exe not found, bug1361. [Patrick Stewart]
Verilator 4.004 2018-10-6
- Add GTKWave FST native tracing, bug1356. [Sergi Granell]
(Verilator developers need to pull the latest vcddiff.)
- Support $past. [Dan Gisselquist]
- Support restrict, bug1350. [Clifford Wolf]
- Rename include/lxt2 to include/gtkwave.
- Fix replication of 64-bit signal change detects.
- Fix Mac OSX 10.13.6 / LLVM 9.1 compile issues, bug1348. [Kevin Kiningham]
- Fix MinGW compile issues, msg2636. [HyungKi Jeong]
Verilator 4.002 2018-09-16
This is a major release. Any patches may require major rework to apply. [Thanks everyone]
- Add multithreaded model generation.
- Add GTKWave LXT2 native tracing, bug1333. [Yu Sheng Lin]
- Note $random has new algorithm; results may vary vs. previous versions.
- Better optimize large always block splitting, bug1244. [John Coiner]
- Add new reloop optimization for repetitive assignment compression.
- Support string.atoi and similar methods, bug1289. [Joel Holdsworth]
- Fix internals to be C++ null-pointer-check clean.
- Fix internals to avoid 'using namespace std'.
- Fix Verilation performance issues, bug1316. [John Coiner]
- Fix clocker attributes to not propagate on concats. [John Coiner]
- Fix first clock edge and --x-initial-edge, bug1327. [Rupert Swarbrick]
- Fix compile error on tracing of string arrays, bug1338. [Iztok Jeras]
- Fix number parsing with newline after radix, bug1340. [George Cuan]
- Fix string ?: conditional type resolution, bug1345. [Iztok Jeras]
- Fix duplicate symbol error on generate tri, bug1347. [Tomas Dzetkulic]
We're glad to announce that Verilator 4.000 is now in beta test and will be formally announced at OrConf 2018
The git tree now contains the beta, please give it a try, and enjoy the main new feature of multithreaded simulation!
- If your git repo was using the 'master' branch (the default) as upstream you need do nothing, you'll now get the 4.000 sources.
- A new 'v3/devel' branch was made pointing to the previous origin/master (with Version 3.xxx) and will only be developed further if another 3.xxx release is required due to a serious issue.
Verilator 3.926 2018-08-22
- Add OBJCACHE envvar support to examples and generated Makefiles.
- Change MODDUP errors to warnings, msg2588. [Marshal Qiao]
- Fix define argument stringification (`"), broke since 3.914. [Joe DErrico]
- Fix to ignore Unicode UTF-8 BOM sequences, msg2576. [HyungKi Jeong]
- Fix function inlining inside certain while loops, bug1330. [Julien Margetts]
Verilog::Language 3.454 2018-08-21
- Support parsing around Cadence protected meta-comments.
- Fix define argument stringification (`"), broke since 3.446. [Joe DErrico]
- Fix to ignore Unicode UTF-8 BOM sequences, msg2576. [HyungKi Jeong]
Verilator 3.924 2018-06-12
- Renamed --profile-cfuncs to --prof-cfuncs.
- Report interface ports connected to wrong interface, bug1294. [Todd Strader]
- When tracing, use scalars on single bit arrays to appease vcddiff.
- Fix parsing "output signed" in V2K port list, msg2540. [James Jung]
- Fix parsing error on bad missing #, bug1308. [Dan Kirkham]
- Fix $clog2 to be in verilog 2005, bug1319. [James Hutchinson]
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Verilog::Language 3.452 2018-04-12
- Fix parsing "output signed" in V2K port list, msg2540. [James Jung]
- Fix GLIBC assertion failure, bug1299. [Filipe Rosset]