Verilog::Language 3.460 2019-01-26
- Fix Verilog::Std being empty on fork, bug1394. [Corey Teffetalor]
Verilog::Language 3.458 2019-01-24
- Add Verilog::Cell::range accessor, bug1393. [Ed Carstens]
- For write_verilog, print any cell parameters.
- Verilator 4.008 2018-12-01
- Support "ref" and "const ref" pins and functions, bug1360. [Jake Longo]
- In --xml-only show the original unmodified names, and add module_files
and cells similar to Verilog-Perl, msg2719. [Kanad Kanhere]
- Add CONTASSREG error on continuous assignments to regs, bug1369. [Peter Gerst]
- Add PROCASSWIRE error on behavioral assignments to wires, msg2737. [Neil Turton]
- Add IMPORTSTAR warning on import::* inside $unit scope.
- Fix --trace-lxt2 compile error on MinGW, msg2711. [HyungKi Jeong]
- Fix hang on bad pattern keys, bug1364. [Matt Myers]
- Fix crash due to cygwin bug in getline, bug1349. [Affe Mao]
- Fix __Slow files getting compiled with OPT_FAST, bug1370. [Thomas Watts]
The 2018 RISC-V design contest has announced all submissions must be submitted only using Verilator.
The contest is to design a RISC-V soft CPU core, run by the RISC-V Foundation, and is sponsored by Google, Antmicro, Lattice Semiconductor and Microsemi. For more details see https://riscv.org/2018contest/
The Veripool website software was upgraded today. If you see any strange behavior, please post an issue.
Verilog::Language 3.456 2018-10-28
- Fix number parsing with newline after radix, bug1340. [George Cuan]
Verilator 4.006 2018-10-27
- Add --pp-comments, msg2700. [Robert Henry]
- For --trace-fst, save enum decoding information, bug1358. [Sergi Granell]
(To visualize enumeration data you must use GTKwave 3.3.95 or newer.)
- For --trace-fst, instead of *.fst.hier, put data into *.fst. [Tony Bybell]
- Fix --trace-lxt2 compile error on MinGW, msg2667. [HyungKi Jeong]
- Fix Windows .exe not found, bug1361. [Patrick Stewart]
Verilator 4.004 2018-10-6
- Add GTKWave FST native tracing, bug1356. [Sergi Granell]
(Verilator developers need to pull the latest vcddiff.)
- Support $past. [Dan Gisselquist]
- Support restrict, bug1350. [Clifford Wolf]
- Rename include/lxt2 to include/gtkwave.
- Fix replication of 64-bit signal change detects.
- Fix Mac OSX 10.13.6 / LLVM 9.1 compile issues, bug1348. [Kevin Kiningham]
- Fix MinGW compile issues, msg2636. [HyungKi Jeong]
Verilator 4.002 2018-09-16
This is a major release. Any patches may require major rework to apply. [Thanks everyone]
- Add multithreaded model generation.
- Add GTKWave LXT2 native tracing, bug1333. [Yu Sheng Lin]
- Note $random has new algorithm; results may vary vs. previous versions.
- Better optimize large always block splitting, bug1244. [John Coiner]
- Add new reloop optimization for repetitive assignment compression.
- Support string.atoi and similar methods, bug1289. [Joel Holdsworth]
- Fix internals to be C++ null-pointer-check clean.
- Fix internals to avoid 'using namespace std'.
- Fix Verilation performance issues, bug1316. [John Coiner]
- Fix clocker attributes to not propagate on concats. [John Coiner]
- Fix first clock edge and --x-initial-edge, bug1327. [Rupert Swarbrick]
- Fix compile error on tracing of string arrays, bug1338. [Iztok Jeras]
- Fix number parsing with newline after radix, bug1340. [George Cuan]
- Fix string ?: conditional type resolution, bug1345. [Iztok Jeras]
- Fix duplicate symbol error on generate tri, bug1347. [Tomas Dzetkulic]
We're glad to announce that Verilator 4.000 is now in beta test and will be formally announced at OrConf 2018
The git tree now contains the beta, please give it a try, and enjoy the main new feature of multithreaded simulation!
- If your git repo was using the 'master' branch (the default) as upstream you need do nothing, you'll now get the 4.000 sources.
- A new 'v3/devel' branch was made pointing to the previous origin/master (with Version 3.xxx) and will only be developed further if another 3.xxx release is required due to a serious issue.