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![[logo]](/img/veripool_small.png) |
| Home |
| News |
| Activity |
| About/Contact |
| Major Tools |
| Dinotrace |
| Verilator |
| Verilog-mode |
| Verilog-Perl |
| Other Tools |
| BugVise |
| CovVise |
| Force-Gate-Sim |
| Gspice |
| IPC::Locker |
| Rsvn |
| SVN::S4 |
| Voneline |
| WFH |
| General Info |
| Papers |
| |
| Home |
| News |
| Activity |
| About/Contact |
| Major Tools |
| Dinotrace |
| Verilator |
| Verilog-mode |
| Verilog-Perl |
| Other Tools |
| BugVise |
| CovVise |
| Force-Gate-Sim |
| Gspice |
| IPC::Locker |
| Rsvn |
| SVN::S4 |
| Voneline |
| WFH |
| General Info |
| Papers |