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Activity

From 07/26/2017 to 08/24/2017

Today

02:50 AM Issue #1191: DPI-C structures seem to come out backwards!
I believe the correct behavior is what you indicated with your "this code works" section, which is what Verilator cur... Wilson Snyder

08/18/2017

03:05 PM Issue #1191: DPI-C structures seem to come out backwards!
I created a regression test (see patch) which reflects the issue. One this this regression does not show, however, i... Rob Stoddard

08/17/2017

11:49 PM Issue #1191: DPI-C structures seem to come out backwards!
Sounds like you might be looking at this yourself, but either way can you please convert this to a test_regress forma... Wilson Snyder
11:30 PM Issue #1191: DPI-C structures seem to come out backwards!
Oh yeah...
Using built-in specs.
COLLECT_GCC=/usr/x86_64-pc-linux-gnu/gcc-bin/5.4.0/gcc
COLLECT_LTO_WRAPPER=/usr...
Rob Stoddard
11:23 PM Issue #1191 (New): DPI-C structures seem to come out backwards!
In my module I have:... Rob Stoddard

08/13/2017

10:09 PM Issue #1187 (Resolved): Internal Error: ../V3Slice.cpp:407: Couldn't find a VarRef on the LHSP of...
Fixed in git towards 3.907.
I added an "lvalue" assertion that flags the (previous) problem earlier, hopefully it ...
Wilson Snyder

08/11/2017

11:09 PM Issue #1190: Fix packed structs in DPI-C
BTW unpacked structs is a much larger issue, so if you want to work on that please put it under a different issue.
Wilson Snyder
11:07 PM Issue #1190 (Resolved): Fix packed structs in DPI-C
I thought other simulators didn't support packed structs, but they seem to. Fixed in git towards 3.907.
Wilson Snyder

08/08/2017

06:44 PM Issue #1190 (Resolved): Fix packed structs in DPI-C
How do I make this a feature request?
In this bug, structs were added as a packed array of logic:
https://www.ver...
Rob Stoddard

08/06/2017

07:33 PM Issue #1189 (WillNotFix): Generate templated classes
Converting parameters to templates is generally not possible given how the SystemVerilog language itself was designed... Wilson Snyder
07:14 PM Issue #1189 (WillNotFix): Generate templated classes
Currently the Verilog can be compiled in a way that ignores the parameters as compile-time constructs. That makes tes... Maciej Piechotka

08/04/2017

04:54 PM Issue #1187: Internal Error: ../V3Slice.cpp:407: Couldn't find a VarRef on the LHSP of an Assign
It turns out that if an inout is unassigned then there are problems. I had two signals in the original design that w... Rob Stoddard
04:52 AM Issue #1187: Internal Error: ../V3Slice.cpp:407: Couldn't find a VarRef on the LHSP of an Assign
It turns out that the issue has something to do with inout ports in the module within which /*verilator public*/ is c... Rob Stoddard

08/03/2017

04:38 PM Issue #1187: Internal Error: ../V3Slice.cpp:407: Couldn't find a VarRef on the LHSP of an Assign
Here is a sample design that shows the error I mentioned... The full build output I'm getting here is:
verilator ...
Rob Stoddard
12:03 AM Issue #1187 (Resolved): Internal Error: ../V3Slice.cpp:407: Couldn't find a VarRef on the LHSP of...
This suddenly happened on a working design when I decided to instrument lines using /*verilator public*/ deep inside ... Rob Stoddard
 

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