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Activity

From 11/16/2017 to 12/15/2017

12/14/2017

12:56 AM Issue #1245: dpi open array support (LRM 35.5.6.1 Open arrays)
Making progress, but not there yet.
Note this is a superset of bug909.
Wilson Snyder
12:52 AM Issue #1249 (AskedReporter): Struct initialisation with data type and member name is not supporte...
Wilson Snyder
12:52 AM Issue #1250 (Resolved): Nested interface reference not found due to inline optimization
This was a bug in the inliner, thanks for the example.
Fixed in git towards 3.917.
>always_comb @(*) begin
T...
Wilson Snyder

12/13/2017

06:22 AM Issue #1250 (Resolved): Nested interface reference not found due to inline optimization
When a parent module instantiates an interface (or passes an interface from its parent) to a child module, nested int... Arjen Roodselaar

12/09/2017

05:03 PM Issue #1248 (Resolved): Large structures expose GCC/clang compile time bug
Workaround added to Verilator in git towards 3.917.
Wilson Snyder
05:03 PM Issue #1248: Large structures expose GCC/clang compile time bug
Matching problem in clang/LLVM:
https://bugs.llvm.org/show_bug.cgi?id=35585
Wilson Snyder

12/08/2017

01:05 AM Issue #1249: Struct initialisation with data type and member name is not supported in 3.916
This is (mostly?) supported, please modify the test_regress/t/t_struct_init.v to show the issue, and pass on another ... Wilson Snyder

12/07/2017

09:48 AM Issue #1249 (AskedReporter): Struct initialisation with data type and member name is not supporte...
I think verilator doesn't support the struct initialisation as below in release 3.916. Do you have plan to support it... Enzo Chi
02:29 AM Issue #1247 (Resolved): ALWCOMBORDER Warnings when driving interfaces
Thanks for the good test.
Fixed in git towards 3.917.
Wilson Snyder
02:26 AM Issue #1248 (Resolved): Large structures expose GCC/clang compile time bug
Very large models cause Verilator to generate classes with a large number of member variables. When these are compile... Wilson Snyder

12/06/2017

12:58 PM Issue #1247 (Resolved): ALWCOMBORDER Warnings when driving interfaces
I am receiving ALWCOMBORDER warnings when I drive an interface signal with another interface signal, inside an always... Josh Redford
04:39 AM Issue #1245: dpi open array support (LRM 35.5.6.1 Open arrays)
Hi Wilson. I am just updated Shunt depository.
Verilator-Shunt example path is: https://github.com/xver/Shunt/tree/...
victor besyakov

11/29/2017

12:14 AM Issue #1246 (Resolved): modport declaration incorrectly treats some outputs as inputs
Simple enough fix, thanks for a complete test case.
Fixed in git towards 3.917.
Wilson Snyder

11/28/2017

05:23 AM Issue #1246 (Resolved): modport declaration incorrectly treats some outputs as inputs
If you have define multiple outputs in a list within a modport, the first is treated as an output, but subsequent ite... Jeff Bush

11/25/2017

08:49 PM Verilator 3.916 Released
Verilator 3.916 2017-11-25
*** Support self-recursive modules, bug659. [Sean Moore, et al]
*** Support $err...
Wilson Snyder
08:48 PM Issue #659 (Closed): Support finitely recursive modules
In 3.916.
Wilson Snyder
08:48 PM Issue #991 (Closed): Assignment to unpacked array causes "Assignment pattern missed initializing ...
In 3.916.
Wilson Snyder
08:48 PM Issue #1110 (Closed): Feature - checking of modport directions in interfaces
In 3.916.
Wilson Snyder
08:48 PM Issue #1232 (Closed): configure check for -faligned-new needs to include header
In 3.916.
Wilson Snyder
08:47 PM Issue #1235 (Closed): Smoke test fails in Debian build
In 3.916.
Wilson Snyder
08:47 PM Issue #1238 (Closed): Verilator concatenation error when passing overflowed value from C++ to ver...
In 3.916.
Wilson Snyder
08:47 PM Issue #1241 (Closed): Signal not driven/used warning when assigning values to modports
In 3.916.
Wilson Snyder

11/23/2017

07:55 PM Issue #991 (Resolved): Assignment to unpacked array causes "Assignment pattern missed initializin...
Finally supporting partial slices, fixed in git towards 3.915.
Wilson Snyder
05:24 PM Issue #1104 (Feature): No support for parameterized interface in module "signal" list.
Wilson Snyder
04:38 PM Issue #795 (Closed): Internal Error: ...: ../V3Slice.cpp:277: ArraySel dtyping failed when resolv...
A warning was added some time earlier as part of another bug. Test added to git so doesn't (re-)break in the future.... Wilson Snyder
04:30 PM Issue #1244: V3Split not splitting
Added some example tests, test_regress/t/t_alw_split_rst.v
Wilson Snyder

11/20/2017

01:28 PM Issue #1245: dpi open array support (LRM 35.5.6.1 Open arrays)
Nice. There was recently a patch to hook Verilator up to MyHDL, wish MyHDL used Shunt.
Wilson Snyder
01:20 PM Issue #1245: dpi open array support (LRM 35.5.6.1 Open arrays)
I am integrating verilator with my DPI library (https://github.com/xver/Shunt).
I do have examples and definitely wi...
victor besyakov

11/19/2017

08:07 PM Issue #1245 (Feature): dpi open array support (LRM 35.5.6.1 Open arrays)
Open arrays are not currently supported, it isn't hugely difficult but the biggest problem would be that at present V... Wilson Snyder
04:06 PM Issue #1245: dpi open array support (LRM 35.5.6.1 Open arrays)
My verilator is: Verilator 3.906 2017-06-22 rev verilator_3_904-11-g1da5a33
I have found 2015 Issue #909 (Feature): ...
victor besyakov
04:00 PM Issue #1245 (Feature): dpi open array support (LRM 35.5.6.1 Open arrays)
trying to compile following:
import "DPI-C" function int shunt_dpi_send_bitN(input int sockid,input int size,inpu...
victor besyakov
12:57 PM Issue #991 (Confirmed): Assignment to unpacked array causes "Assignment pattern missed initializi...
Wilson Snyder
12:56 PM Issue #1011 (Confirmed): Can't reference interface functions inside of generate blocks
Wilson Snyder
12:54 PM Issue #1008 (Confirmed): Incorrect results with partially out-of-bounds part select (re-opened)
Wilson Snyder
12:53 PM Issue #1184 (Feature): Verilator doesn't detect multiple assignment
Wilson Snyder
01:43 AM Issue #1244 (Confirmed): V3Split not splitting
Wilson Snyder

11/18/2017

10:56 PM Issue #1192 (WillNotFix): Can't override parameter defined as "type xxxx" through command line wi...
As far as I can tell this isn't supported in other simulators, so unless someone wants to commit a relatively complic... Wilson Snyder
10:52 PM Issue #1110 (Resolved): Feature - checking of modport directions in interfaces
Fixed in git towards 3.915.
Wilson Snyder
10:50 PM Issue #1199 (NotEnoughInfo): Can't called by start-process correctly
Didn't hear back, presumably you got it working.
Wilson Snyder
10:48 PM Issue #798 (Closed): verilator does not detect dimension mismatch error
This was fixed somewhere along the way.
%Error: t/t_array_mism_bad.v:16: VARREF 't.ready_to_issue_addr' is not an...
Wilson Snyder
10:43 PM Issue #659 (Resolved): Support finitely recursive modules
(Finally) fixed in git towards 3.915.
Wilson Snyder

11/16/2017

06:08 PM Issue #1244: V3Split not splitting
Whoops, here's the above code sample with formatting:... John Coiner
06:06 PM Issue #1244 (Confirmed): V3Split not splitting
We have an input like this:
always @(posedge clk) begin
if ((rst_l == 0)) begin
reg1 <= 1'b0;
...
John Coiner
 

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