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Activity

From 02/23/2019 to 03/24/2019

Today

01:15 AM Issue #1383 (Closed): Support SystemVerilog void casts & warn if not present
In 4.012.
Wilson Snyder
01:15 AM Issue #1384 (Closed): File-extension language option not consistently applied
In 4.012.
Wilson Snyder
01:15 AM Issue #1396 (Closed): Verilator random number generated seeded with lrand48(), which isn't determ...
In 4.012.
Wilson Snyder
01:15 AM Issue #1400 (Closed): Bug: verilator sometimes fails to detect electrical short
In 4.012.
Wilson Snyder
01:15 AM Issue #1406 (Closed): Mixed _WIN32/WIN32 definitions causes compiler error over mkdir defintion i...
In 4.012.
Wilson Snyder
01:15 AM Verilator 4.012 Released
Verilator 4.012 2019-3-23
*** Add +verilator+seed, bug1396. [Stan Sokorac]
*** Support $fread. [Leendert v...
Wilson Snyder

03/21/2019

11:20 AM Issue #1402: Compile verilator to webassembly
>But you also need to apt-get install libfl-dev (https://packages.ubuntu.com/bionic/amd64/libfl-dev/filelist).
Ubu...
Wilson Snyder
07:13 AM Issue #1402: Compile verilator to webassembly
Under Ubuntu 18.04LTS (bionic), the likely issue is that [[Installing]] implies the dependencies are:... Tyrel Newton

03/15/2019

11:12 AM Issue #1409: Incorrect Result of Cascading Module Using Generate Statement
Thanks! It works! Xusine Lin

03/14/2019

10:04 PM Issue #1409 (NoFixNeeded): Incorrect Result of Cascading Module Using Generate Statement
>%Warning-STMTDLY: bsg_nonsynth_clock_gen.v:15: Unsupported: Ignoring delay on this delayed statement.
Verilator i...
Wilson Snyder
01:28 PM Issue #1409: Incorrect Result of Cascading Module Using Generate Statement
In spite of the disorder I packed my code into the attachment. Xusine Lin
01:23 PM Issue #1409 (NoFixNeeded): Incorrect Result of Cascading Module Using Generate Statement
Hi. I use Verilator to verify a ripple carry adder formed by a series of full adders generated by generate statement ... Xusine Lin
10:09 AM Issue #1408: Support concatenation select
Wilson Snyder wrote:
> Two of the big three simulators do not appear to support select of concatenation of expressio...
Alexander Junk

03/13/2019

11:52 PM Issue #1408 (Feature): Support concatenation select
Two of the big three simulators do not appear to support select of concatenation of expressions, until they do I'm re... Wilson Snyder
06:38 PM Issue #1408 (Feature): Support concatenation select
When trying to verilate multimux_out_2.v with... Alexander Junk

03/11/2019

08:33 AM Issue #1405: Port defined as a net but used as a reg is not flagged as an error
Unfortunately I inherited the design with the construct above and it's a pure Verilog implementation, not SystemVeril... Lloyd Gomez

03/10/2019

07:37 PM Issue #1405 (WillNotFix): Port defined as a net but used as a reg is not flagged as an error
Looked further at this. In System Verilog this assignment is legal (as it's an sized type); note you didn't ask model... Wilson Snyder
04:27 PM Issue #1405 (Feature): Port defined as a net but used as a reg is not flagged as an error
Looking at fixes...
Wilson Snyder
07:12 PM Issue #1383 (Resolved): Support SystemVerilog void casts & warn if not present
Fixed in git towards 4.012.
Also added IGNOREDRETURN warning when no cast present, which is required by IEEE.
Wilson Snyder
06:21 PM Issue #1377 (NotEnoughInfo): Segmentation Fault when tracing is enabled
Sounds like you got this working a while ago.
Closing due to not getting a test case or patch, if you have one ple...
Wilson Snyder
06:09 PM Issue #1384 (Resolved): File-extension language option not consistently applied
Fixed in git towards 4.012.
Wilson Snyder
04:26 PM Issue #1355 (NotEnoughInfo): Multi-thread example: --threads 1 (compile error)
Didn't hear back so closing this for now, if you figured it out please post back here. Thanks.
Wilson Snyder

03/08/2019

11:14 PM Issue #1407: facing a error for verilatedvcdsc
using
verilator -sc --exe -Wall --trace left.v sc_main.cpp
make -C obj_dir -f Vleft.mk
With the curren...
Wilson Snyder
05:19 PM Issue #1407: facing a error for verilatedvcdsc
i am attaching files for which i am compiling . that is verilog rtl file left.v , testbench sc_main.cpp , text file f... divyakumar shah

03/07/2019

11:20 PM Issue #1407: facing a error for verilatedvcdsc
I test ok with 20181013. Your file looks ok. Please attach a complete tarball example - the file you attached doesn... Wilson Snyder
04:59 PM Issue #1407: facing a error for verilatedvcdsc
for systemc version
#define SYSTEMC_2_3_3
#define SYSTEMC_VERSION 20181013
divyakumar shah
04:56 PM Issue #1407: facing a error for verilatedvcdsc
i am not missing systemc.h in my sc_main file
here my code
#include <systemc.h>
#include <Vleft.h>
#include <ve...
divyakumar shah
12:10 AM Issue #1407: facing a error for verilatedvcdsc
BTW if that doesn't work, to prefetch the next question please tell me the SYSTEMC_VERSION (from systemc's sysc/kerne... Wilson Snyder
12:07 AM Issue #1407 (AskedReporter): facing a error for verilatedvcdsc
I suspect you are missing a #include <systemc.h> in your sc_main file (see examples/tracing_sc/sc_main.cpp). If that... Wilson Snyder

03/06/2019

03:16 PM Issue #1407 (AskedReporter): facing a error for verilatedvcdsc
i am putting forward an error which i am facing... divyakumar shah

03/05/2019

02:39 PM Issue #1406: Mixed _WIN32/WIN32 definitions causes compiler error over mkdir defintion in verilat...
Thanks! Works in my environment. Benjamin Gartner
01:30 AM Issue #1406 (Resolved): Mixed _WIN32/WIN32 definitions causes compiler error over mkdir defintion...
You're right, these two should be changed from WIN32 to _WIN32, everywhere else _WIN32 was used.
Fixed in git towa...
Wilson Snyder
12:51 AM Issue #1406: Mixed _WIN32/WIN32 definitions causes compiler error over mkdir defintion in verilat...
Oops.
I actually meant ...
Benjamin Gartner

03/04/2019

11:33 PM Issue #1406 (AskedReporter): Mixed _WIN32/WIN32 definitions causes compiler error over mkdir defi...
For the fixed version did you mean?... Wilson Snyder
08:21 PM Issue #1406 (Closed): Mixed _WIN32/WIN32 definitions causes compiler error over mkdir defintion i...
I get the following compile error when compiling verilated.cpp in Visual Studio.
Error C2039 'mkdir': is not a membe...
Benjamin Gartner

03/02/2019

01:19 AM Issue #1399: x-assign and x-initial 'unique' setting appears not to work
Got it! I can confirm that it works now. Thanks! Stan Sokorac
01:08 AM Issue #1399: x-assign and x-initial 'unique' setting appears not to work
You need to call Verilated::commandArgs before you construct the model, I'll clarify this in the docs. Wilson Snyder

02/28/2019

02:19 PM Issue #1399: x-assign and x-initial 'unique' setting appears not to work
I've fixed the second display... assignx does indeed work (I was printing the uninit value twice), but uninitialized ... Stan Sokorac
03:20 AM Issue #1400: Bug: verilator sometimes fails to detect electrical short
Wilson Snyder wrote:
> Fixed in git towards 4.012.
Thanks!
Will Korteland
02:07 AM Issue #1400 (Resolved): Bug: verilator sometimes fails to detect electrical short
Fixed in git towards 4.012.
Wilson Snyder
12:27 AM Issue #1405 (WillNotFix): Port defined as a net but used as a reg is not flagged as an error
Hello,
I have a block with an output port that's supposed to be a declared as a reg, but I forgot to do so and Ver...
Lloyd Gomez

02/26/2019

11:58 PM Issue #1399 (NoFixNeeded): x-assign and x-initial 'unique' setting appears not to work
Running the model with "+verilator+seed+50 +verilator+rand+reset+2" this seems to print random values for me, perhaps... Wilson Snyder
04:24 PM Issue #1402 (NoFixNeeded): Compile verilator to webassembly
Looks like you don't have "flex" installed, that file comes with flex.
If you're trying to get a new compiler goin...
Wilson Snyder
 

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