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Activity

From 05/26/2013 to 06/24/2013

06/24/2013

02:43 AM Issue #659 (Feature): Support finitely recursive modules
Interesting, first time I've seen this sort of recursion used for something that isn't just completely silly.
To V...
Wilson Snyder
01:54 AM Issue #659 (Closed): Support finitely recursive modules
I'm getting an error thrown when trying to create recursively instantiated modules in Verilog.
@-Info-Loop: 0x92f9...
Sean Moore

06/21/2013

09:11 AM Issue #658: SystemVerilog interfaces: Internal error when connecting interfaces
Hi Wilson, yes indeed sadly I cannot recreate the internal error with our simplified example, so there is nothing for... Ed Lander
12:28 AM Issue #658: SystemVerilog interfaces: Internal error when connecting interfaces
Ok, so the last example you gave already passes on git head, right? So I'm not sure if there's something for me to l... Wilson Snyder

06/19/2013

02:34 PM Issue #658: SystemVerilog interfaces: Internal error when connecting interfaces
I've replicated our example almost exactly now (file attached), but Verilator is happy with it (cannot recreate inter... Ed Lander
01:58 PM Issue #658: SystemVerilog interfaces: Internal error when connecting interfaces
Example updated (now with two instances of an interface propagating down through two levels of hierarchy). Clean outp... Ed Lander
01:13 PM Issue #658: SystemVerilog interfaces: Internal error when connecting interfaces
Clean example attached (to be made more complex). Ed Lander
11:45 AM Issue #658: SystemVerilog interfaces: Internal error when connecting interfaces
Typo in example corrected. Ed Lander
11:17 AM Issue #658: SystemVerilog interfaces: Internal error when connecting interfaces
Revised example attached. Internal error not repeated; i'll try recoding our complex example ... Ed Lander

06/18/2013

07:01 PM Issue #657: Read Parmetarized Verilog File
See the BUGS section in the end of the manual for how to create a test.
[http://www.veripool.org/projects/verilato...
Joe Eiler
04:36 PM Issue #657: Read Parmetarized Verilog File
Would you please tell me where in the Document? I can not find it!
Thanks
Amir Yazdanbakhsh
04:36 PM Issue #657: Read Parmetarized Verilog File
This is an incomplete example - please provide a complete example that has been checked on another simulator, see the... Wilson Snyder
04:22 PM Issue #657 (NotEnoughInfo): Read Parmetarized Verilog File
Hi,
I was trying to read a parameterized Verilog file with Verilator. But it seems it generates and error.
Attach...
Amir Yazdanbakhsh
04:37 PM Issue #658: SystemVerilog interfaces: Internal error when connecting interfaces
Important clarification: whilst we define multiple / nested interfaces, our design isn't actually using the nested st... Ed Lander
04:30 PM Issue #658 (NotEnoughInfo): SystemVerilog interfaces: Internal error when connecting interfaces
Hi,
We are seeing an internal error when connecting SystemVerilog interfaces. Verilator happily compiles the inter...
Ed Lander

06/17/2013

08:29 PM Issue #655: vpi memory iterator
I had just made t_vpI_var match the return values, assuming your fixes were ok. If that's not right a fix would be a... Wilson Snyder
07:57 PM Issue #655: vpi memory iterator
Oooops. Didn't mean to repost that last comment. Sorry.
But while I'm here I'll point out that the t_vpi_var issue...
Rich Porter
07:51 PM Issue #655: vpi memory iterator
I've ported the t_vpi_memory test to iverilog, and it passes for both verilator and iverilog which increases my confi... Rich Porter

06/13/2013

12:06 PM Issue #655 (Resolved): vpi memory iterator
Pushed to git towards 3.851. Thanks again for patching!
Wilson Snyder
11:06 AM Issue #655: vpi memory iterator
Great, I'll merge your changes then do the other name cleanup.
Wilson Snyder
10:12 AM Issue #655: vpi memory iterator
I've ported the t_vpi_memory test to iverilog, and it passes for both verilator and iverilog which increases my confi... Rich Porter

06/12/2013

08:10 PM Issue #655: vpi memory iterator
I've added a test case to the branch - test_regress/t_vpi_memory, the other test case I mentioned previously was just... Rich Porter

06/06/2013

10:29 PM Issue #655: vpi memory iterator
The bug seems reasonable. The test case wasn't in your branch though so I couldn't test it to make sure.
I'm not ...
Wilson Snyder
03:38 AM Issue #613 (Resolved): Better gated clock support
Pushed to git towards 3.851.
Gave this a good tryout, seems stable. Good job debugging this; it's quite impressiv...
Wilson Snyder

06/05/2013

01:16 PM Issue #655 (Closed): vpi memory iterator
I think that the iterator returned by vpi_iterate with a type of vpiMemoryWord is incorrect. The diagram in IEEE 1364... Rich Porter

06/03/2013

11:08 PM Issue #654 (Closed): VCD handling regression test failure
Passed on my system, but valgrind suggested the problem.
Fixed in git towards 3.851.
Wilson Snyder
06:04 PM Issue #654 (Closed): VCD handling regression test failure
The t_trace_cat_renew fails with the current git master (commit ID 7a65df763645ece622ef7ae43b5298a902bdb3fd). It seem... Jeremy Bennett
05:40 PM Issue #613: Better gated clock support
Having worked with Jie on this, I believe it seems the problem is caused by the extra loop added for internally gener... Jeremy Bennett

06/02/2013

06:55 PM Issue #645 (Closed): VL_INW and VL_OUTW macros require 4 arguments, but only 3 given
In 3.850.
Wilson Snyder
06:54 PM Issue #652 (Closed): Width mismatch problem
In 3.850.
Wilson Snyder
06:54 PM Issue #651 (Closed): Different versions of GCC cause Verilator generated models to succeed or fail
In 3.850.
Wilson Snyder
06:54 PM Issue #621 (Closed): Enable duplicate gate elimination in ~3.848.
In 3.850.
Wilson Snyder
06:54 PM Issue #102 (Closed): Support "interface" and "endinterface" keywords
In 3.850.
Wilson Snyder
06:52 PM Verilator 3.850 Released
Verilator 3.850 2013-06-02
** Support interfaces and modports, bug102. [Byron Bradley, Jeremy Bennett]
*** ...
Wilson Snyder

05/30/2013

09:57 PM Issue #653 (Assigned): vcddiff tests fail with latest gpl-cver vcddiff
Comment out for now. I know the vcddiff author and asked if he or I can make a new release.
Wilson Snyder
07:45 PM Issue #653 (Closed): vcddiff tests fail with latest gpl-cver vcddiff
I found regression tests failing with the latest version of _vcddiff_. The problem is due to it putting out a welcome... Jeremy Bennett

05/28/2013

02:39 AM Issue #621 (Resolved): Enable duplicate gate elimination in ~3.848.
Enabled in git towards 3.848.
Wilson Snyder
01:41 AM Issue #102 (Resolved): Support "interface" and "endinterface" keywords
Interface support added to git towards 3.848.
Interfaces and modports, including with generated data types are sup...
Wilson Snyder
 

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