From 11/11/2016 to 12/10/2016
- 12:25 PM Issue #1118 (WillNotFix): Clocking block
- Verilator does not support SystemVerilog verification constructs, sorry.
If everything works except this, and you'...
- 04:33 PM Issue #1118: Clocking block
- Sorry, here is the code ...
- 04:29 PM Issue #1118 (WillNotFix): Clocking block
I am writing some system verilog testbench. However, when I create a clocking block, I obtain the following error
- 08:02 PM Issue #1116 (Closed): Default make install on Ubuntu puts bin & data in incompatible locations
- Docs updated in git, thanks for suggesting that.
- 07:49 PM Issue #1117 (Resolved): Can't compile with "--assert" for files with "unique casez"
- Indeed had never handled inside casez, thanks for the test. Fixed in git towards 3.891.
- 10:21 AM Issue #1117 (Closed): Can't compile with "--assert" for files with "unique casez"
- Verilator 3.886 2016-07-30 rev verilator_3_884-13-gb4a7e46
Can't compile file with "unique casez" with "--assert"
- 01:42 AM Issue #1044: Internal error when doing V3Simulate on for loop inside for loop
- Thanks for the test case, straight forward now that I know where to look.
Fixed in git towards 3.891.
- 11:56 AM Issue #1044: Internal error when doing V3Simulate on for loop inside for loop
- We've finally set aside some time to create a small test case for this issue. It all seems to be related to the size ...
- 10:48 PM Issue #1116: Default make install on Ubuntu puts bin & data in incompatible locations
- Then it seems the documentation could use an update:...
- 09:32 PM Issue #1116 (AskedReporter): Default make install on Ubuntu puts bin & data in incompatible locat...
- First, please make sure you're using the most recent version as there was a related install bug in an earlier release...
- 06:19 PM Issue #1116 (Closed): Default make install on Ubuntu puts bin & data in incompatible locations
- `make install` puts verilator_bin in $(DESTDIR)$(bindir)/verilator_bin but the data (especially include/verilator.mk)...
- 09:38 PM Issue #1115: Import statement not recognized
- I've updated the documentation in git.
The name of the files in obj_dir will be based on the first file, but will ...
- 04:49 PM Issue #1115: Import statement not recognized
- Well that's the thing -- I did originally put it on the command line (albeit accidentally) via *.v. I also tried:
- 01:23 PM Issue #1115 (NoFixNeeded): Import statement not recognized
- SystemVerilog specification requires you to declare all packages before you use them. Either put common.v on the comm...
- 07:25 PM Issue #1115 (NoFixNeeded): Import statement not recognized
- I'm using Verilator built from head (11/26/2016), and 1800-2012 SystemVerilog....
- 04:02 PM Issue #1099 (Closed): Crash with struct combined with parameters
- In 3.890.
- 04:02 PM Issue #1097 (Closed): Interface declaration typo gives a misleading internal error
- In 3.890.
- 04:02 PM Issue #1103 (Closed): Verilator fails to build with flex-2.6.2
- In 3.890.
- 04:01 PM Issue #1098 (Closed): Coverage Declarations does not honor output split cfuncs
- In 3.890.
- 04:01 PM Verilator 3.890 Released
- Verilator 3.890 2016-11-25
*** Honor --output-split on coverage constructors, bug1098. [Johan Bjork]
- 09:14 PM Issue #1112 (Closed): passing an interface to a non-interface port causes internal error
- Low priority. Happy to fix it but need some advice on what stage would be best suited to detect this:...
- 05:29 PM Issue #1111 (AskedReporter): build requires pod2man & creating a recipe for Yoctor
- Thanks for working on this. I'm not sure if any changes are needed in verilator or not, but if so we'd welcome a pat...
- 06:05 PM Issue #1111 (NoFixNeeded): build requires pod2man & creating a recipe for Yoctor
- Helo All,
Created an Image for a Raspberry Pi 2B using yocto.
Downloaded the source code
- 06:26 PM Issue #934: Boolean expression in sensitivity list unsupported
- Hi Wilson-
It be great if the parser supported this syntax and then errored out during elaboration of some other s...
- 12:41 AM Issue #1110 (Closed): Feature - checking of modport directions in interfaces
- Verilator currently does not throw an error when driving a signal which is defined to be an input in an interface mod...
- 05:49 PM Issue #831: Gate optimizer: Can't replace lvalue assignments with const var
- Sorry you're still seeing this. The error specifically is that the optimizer sees duplicate logic and is basically at...
- 03:15 PM Issue #831: Gate optimizer: Can't replace lvalue assignments with const var
- I have run into this error periodically. It definitely comes and goes so to speak. My observation is that it is rel...
- 05:29 PM Issue #1109 (Feature): Easier trace of only a submodule
- At present you can only trace from the top down. You can specify which modules to include/exclude using the pragmas o...
- 03:45 PM Issue #1109 (NoFixNeeded): Easier trace of only a submodule
- The issue is, I want to store the trace (vcd) of a submodule rather than the top module. If I run verilator with "--t...
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