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Activity

From 10/18/2017 to 11/16/2017

11/16/2017

06:08 PM Issue #1244: V3Split not splitting
Whoops, here's the above code sample with formatting:... John Coiner
06:06 PM Issue #1244 (Closed): V3Split not splitting
We have an input like this:
always @(posedge clk) begin
if ((rst_l == 0)) begin
reg1 <= 1'b0;
...
John Coiner

11/15/2017

01:11 AM Issue #1241 (Resolved): Signal not driven/used warning when assigning values to modports
Fixed in git towards 3.915.
Also added error when modport inputs are assigned to.
Wilson Snyder

11/07/2017

01:14 PM Issue #1241: Signal not driven/used warning when assigning values to modports
Todd Strader wrote:
> Your master modport's signal is an input, yet you are assigning it in your example module. Tr...
Laurens van Dam

11/06/2017

02:46 PM Issue #1238: Verilator concatenation error when passing overflowed value from C++ to verilog inpu...
Thanks Wilson! I will have a try on the new feature.
Junyi
Junyi Xie
02:50 AM Issue #1238 (Resolved): Verilator concatenation error when passing overflowed value from C++ to v...
Fixed to add assertion when VL_DEBUG is enabled.
Wilson Snyder
10:16 AM Issue #1241: Signal not driven/used warning when assigning values to modports
Your master modport's signal is an input, yet you are assigning it in your example module. Try swapping master and s... Todd Strader
08:00 AM Issue #1241 (Closed): Signal not driven/used warning when assigning values to modports
Hi Verilator team,
I have observed certain behaviour with Verilator of which I am not sure if this intended or not...
Laurens van Dam
02:56 AM Issue #1109 (NoFixNeeded): Easier trace of only a submodule
Closing due to age, as noted a .vlt file is the way to do this, or provide a patch to improve it, thanks.
Wilson Snyder
02:55 AM Issue #1093 (NoFixNeeded): Speed up --no-decoration mode for V3OutputFormatter
I think this was relatively abandoned beyond the alignment change which was pushed earlier, feel free to reopen a new... Wilson Snyder
02:52 AM Issue #1235 (Resolved): Smoke test fails in Debian build
Different fix that should have similar effect to git a week or so ago towards 3.913.
Wilson Snyder

10/26/2017

05:03 PM Issue #1238: Verilator concatenation error when passing overflowed value from C++ to verilog inpu...
And probably make it opt-in / opt-out so user can do the performance-safety tradeoff Junyi Xie
05:02 PM Issue #1238: Verilator concatenation error when passing overflowed value from C++ to verilog inpu...
3 can be good. We should not let over-width inputs still pass to input port. If this happens, maybe throwing an excep... Junyi Xie

10/24/2017

10:25 PM Issue #1238 (Assigned): Verilator concatenation error when passing overflowed value from C++ to v...
Yes, that's true. There are several ways to debate handling this.
1. No change to verilator, just note it in the ...
Wilson Snyder

10/23/2017

10:39 PM Issue #1238 (Closed): Verilator concatenation error when passing overflowed value from C++ to ver...
Hi Verilator team,
I have found something related to memory accessing in Verilator.
When the value from C++ inp...
Junyi Xie
 

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