Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  IPC::Locker
  Parallel::Forker
  Voneline
General Info
  Papers

Activity

From 10/25/2017 to 11/23/2017

11/23/2017

07:55 PM Issue #991 (Resolved): Assignment to unpacked array causes "Assignment pattern missed initializin...
Finally supporting partial slices, fixed in git towards 3.915.
Wilson Snyder
05:24 PM Issue #1104 (Feature): No support for parameterized interface in module "signal" list.
Wilson Snyder
04:38 PM Issue #795 (Closed): Internal Error: ...: ../V3Slice.cpp:277: ArraySel dtyping failed when resolv...
A warning was added some time earlier as part of another bug. Test added to git so doesn't (re-)break in the future.... Wilson Snyder
04:30 PM Issue #1244: V3Split not splitting
Added some example tests, test_regress/t/t_alw_split_rst.v
Wilson Snyder

11/20/2017

01:28 PM Issue #1245: dpi open array support (LRM 35.5.6.1 Open arrays)
Nice. There was recently a patch to hook Verilator up to MyHDL, wish MyHDL used Shunt.
Wilson Snyder
01:20 PM Issue #1245: dpi open array support (LRM 35.5.6.1 Open arrays)
I am integrating verilator with my DPI library (https://github.com/xver/Shunt).
I do have examples and definitely wi...
victor besyakov

11/19/2017

08:07 PM Issue #1245 (Feature): dpi open array support (LRM 35.5.6.1 Open arrays)
Open arrays are not currently supported, it isn't hugely difficult but the biggest problem would be that at present V... Wilson Snyder
04:06 PM Issue #1245: dpi open array support (LRM 35.5.6.1 Open arrays)
My verilator is: Verilator 3.906 2017-06-22 rev verilator_3_904-11-g1da5a33
I have found 2015 Issue #909 (Feature): ...
victor besyakov
04:00 PM Issue #1245 (Closed): dpi open array support (LRM 35.5.6.1 Open arrays)
trying to compile following:
import "DPI-C" function int shunt_dpi_send_bitN(input int sockid,input int size,inpu...
victor besyakov
12:57 PM Issue #991 (Confirmed): Assignment to unpacked array causes "Assignment pattern missed initializi...
Wilson Snyder
12:56 PM Issue #1011 (Confirmed): Can't reference interface functions inside of generate blocks
Wilson Snyder
12:54 PM Issue #1008 (Confirmed): Incorrect results with partially out-of-bounds part select (re-opened)
Wilson Snyder
12:53 PM Issue #1184 (Feature): Verilator doesn't detect multiple assignment
Wilson Snyder
01:43 AM Issue #1244 (Confirmed): V3Split not splitting
Wilson Snyder

11/18/2017

10:56 PM Issue #1192 (WillNotFix): Can't override parameter defined as "type xxxx" through command line wi...
As far as I can tell this isn't supported in other simulators, so unless someone wants to commit a relatively complic... Wilson Snyder
10:52 PM Issue #1110 (Resolved): Feature - checking of modport directions in interfaces
Fixed in git towards 3.915.
Wilson Snyder
10:50 PM Issue #1199 (NotEnoughInfo): Can't called by start-process correctly
Didn't hear back, presumably you got it working.
Wilson Snyder
10:48 PM Issue #798 (Closed): verilator does not detect dimension mismatch error
This was fixed somewhere along the way.
%Error: t/t_array_mism_bad.v:16: VARREF 't.ready_to_issue_addr' is not an...
Wilson Snyder
10:43 PM Issue #659 (Resolved): Support finitely recursive modules
(Finally) fixed in git towards 3.915.
Wilson Snyder

11/16/2017

06:08 PM Issue #1244: V3Split not splitting
Whoops, here's the above code sample with formatting:... John Coiner
06:06 PM Issue #1244 (Closed): V3Split not splitting
We have an input like this:
always @(posedge clk) begin
if ((rst_l == 0)) begin
reg1 <= 1'b0;
...
John Coiner

11/15/2017

01:11 AM Issue #1241 (Resolved): Signal not driven/used warning when assigning values to modports
Fixed in git towards 3.915.
Also added error when modport inputs are assigned to.
Wilson Snyder

11/07/2017

01:14 PM Issue #1241: Signal not driven/used warning when assigning values to modports
Todd Strader wrote:
> Your master modport's signal is an input, yet you are assigning it in your example module. Tr...
Laurens van Dam

11/06/2017

02:46 PM Issue #1238: Verilator concatenation error when passing overflowed value from C++ to verilog inpu...
Thanks Wilson! I will have a try on the new feature.
Junyi
Junyi Xie
02:50 AM Issue #1238 (Resolved): Verilator concatenation error when passing overflowed value from C++ to v...
Fixed to add assertion when VL_DEBUG is enabled.
Wilson Snyder
10:16 AM Issue #1241: Signal not driven/used warning when assigning values to modports
Your master modport's signal is an input, yet you are assigning it in your example module. Try swapping master and s... Todd Strader
08:00 AM Issue #1241 (Closed): Signal not driven/used warning when assigning values to modports
Hi Verilator team,
I have observed certain behaviour with Verilator of which I am not sure if this intended or not...
Laurens van Dam
02:56 AM Issue #1109 (NoFixNeeded): Easier trace of only a submodule
Closing due to age, as noted a .vlt file is the way to do this, or provide a patch to improve it, thanks.
Wilson Snyder
02:55 AM Issue #1093 (NoFixNeeded): Speed up --no-decoration mode for V3OutputFormatter
I think this was relatively abandoned beyond the alignment change which was pushed earlier, feel free to reopen a new... Wilson Snyder
02:52 AM Issue #1235 (Resolved): Smoke test fails in Debian build
Different fix that should have similar effect to git a week or so ago towards 3.913.
Wilson Snyder

10/26/2017

05:03 PM Issue #1238: Verilator concatenation error when passing overflowed value from C++ to verilog inpu...
And probably make it opt-in / opt-out so user can do the performance-safety tradeoff Junyi Xie
05:02 PM Issue #1238: Verilator concatenation error when passing overflowed value from C++ to verilog inpu...
3 can be good. We should not let over-width inputs still pass to input port. If this happens, maybe throwing an excep... Junyi Xie
 

Also available in: Atom