Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Activity

From 01/30/2018 to 02/28/2018

02/28/2018

12:01 PM Issue #1244 (Resolved): V3Split not splitting
John Coiner provided an excellent patch which is merged into git develop-v4 branch, towards version 4.000.
Thanks ...
Wilson Snyder

02/26/2018

09:26 AM Issue #1281 (Resolved): Trig functions
Pushed patch to git (with minor space changes) towards 3.922.
Thanks again for your effort.
Wilson Snyder
09:05 AM Issue #1278 (Confirmed): Unsupported LHS tristate construct: ARRAYSEL
Due to how the code currently works supporting arrays will be painful, so is unlikely to be improved in the short ter... Wilson Snyder

02/25/2018

02:31 PM Issue #1278: Unsupported LHS tristate construct: ARRAYSEL
You can use packed arrays instead:
inout [NumBusses-1:0][7:0]p_busses ;
Udi Finkelstein

02/21/2018

04:51 PM Issue #1281: Trig functions
Do you mean the C++ math functions? None of the @<cmath>@ functions raise exceptions, they just return @NaN@ or @+-in... Patrick Stewart
04:06 PM Issue #1281: Trig functions
Nicely done. Do any if these return exceptions with e.g. 0 inputs? If so can you please have the test check that, and... Wilson Snyder
04:22 AM Issue #1281: Trig functions
Sorry, that should be: "https://github.com/patstew/verilator/commit/f3fa47a6791815619b7bf749be2be92d9cc985ac":https:/... Patrick Stewart
04:18 AM Issue #1281 (Closed): Trig functions
I've added the missing system trig functions ($sin() etc) here: http://github.com/patstew/verilator/commit/ae1139d73e... Patrick Stewart

02/15/2018

05:58 PM Issue #1278: Unsupported LHS tristate construct: ARRAYSEL
What I provided was a trifle example, as you probably know, I am writing software that generates RTL dynamically. Al... Rob Stoddard
12:18 PM Issue #1278: Unsupported LHS tristate construct: ARRAYSEL
Any message with "Unsupported" generally means the language supports something but Verilator does not.
In this cas...
Wilson Snyder

02/14/2018

08:12 PM Issue #1278 (Confirmed): Unsupported LHS tristate construct: ARRAYSEL
I am wondering what this actually means, I was under the impression that this is legal SystemVerilog. I am trying to... Rob Stoddard
12:25 PM Issue #1276: vcd trace splits packed data type when it comes through a typedef
I don't see this behavior. Please add to test_regress/t/t_trace_complex.v to show the problem.
Wilson Snyder
12:17 PM Issue #1277 (WillNotFix): instantiate SystemC model in Verilog dut
You cannot have SystemC underneath Verilog, unless you use DPI/VPI to make some sort of harness similar to what you w... Wilson Snyder
05:48 AM Issue #1277 (WillNotFix): instantiate SystemC model in Verilog dut
Hello,
I'm trying to verilate a system with the following hierarchy:
sim_main.cpp as a testbench instantiating ...
Steven Milburn

02/13/2018

07:59 PM Issue #1276 (NotEnoughInfo): vcd trace splits packed data type when it comes through a typedef
In our verilog code, we have something similar to the below typedef:... Christopher Russell
07:50 PM Issue #1275: genvar in always_comb doesn't fail or lint warn during compile when not in a generat...
I might look into it after I get some downtime at work. I'll reference the original issue for what you may have alre... Christopher Russell

02/12/2018

03:06 AM Issue #1275 (Duplicate): genvar in always_comb doesn't fail or lint warn during compile when not ...
This is a duplicate of bug408. If you're interested in looking at fixes, please update there, otherwise perhaps I've... Wilson Snyder

02/11/2018

11:53 PM Issue #1275 (Duplicate): genvar in always_comb doesn't fail or lint warn during compile when not ...
I think the language spec only allows for genvar variable usage in always_comb and assign when under a generate scope... Christopher Russell
12:11 AM Issue #1274 (Resolved): Pullup / Pulldown on arrays causes internal crash
Two problems, first it should have printed an unsupported error. Then I presume you want it supported.
Both fixed ...
Wilson Snyder

02/08/2018

07:02 PM Issue #1274 (Closed): Pullup / Pulldown on arrays causes internal crash
I found this at first with a generate statement, so I thought it had to do with generate statements. But after crea... Rob Stoddard

02/02/2018

01:17 AM Issue #1265 (Closed): Fix status code of generated Makefile
In 3.920.
Wilson Snyder
01:17 AM Issue #1264 (Closed): verilator generates bad C++ with --public for module binds
In 3.920.
Wilson Snyder
01:08 AM Issue #1264 (Resolved): verilator generates bad C++ with --public for module binds
Thanks for the test, fixed in git towards 3.919.
Wilson Snyder
01:17 AM Issue #1267 (Closed): Unlinked error on input-only tristate comparisons
In 3.920.
Wilson Snyder
01:17 AM Issue #1261 (Closed): verilator generates bad C++ with --public for real module parameters
In 3.920.
Wilson Snyder
01:16 AM Issue #1260 (Closed): verilator runs out of memory at gateAll
In 3.920.
Wilson Snyder
01:16 AM Issue #1268 (Closed): tracing_x examples do not generate proper waveform with verilator 3.918
In 3.920.
Wilson Snyder
01:16 AM Issue #1269 (Closed): Verilator supports assert but not assume
In 3.920.
Wilson Snyder
01:15 AM Verilator 3.920 released
Verilator 3.920 2018-02-01
** Moving forward, use the git "stable" branch to track the latest release,
a...
Wilson Snyder

02/01/2018

11:39 PM Issue #1264: verilator generates bad C++ with --public for module binds
Apparently there is no any tests for bind of interface.
Testcase is attached.
Output with compile error:
<pr...
Alex Solomatnikov

01/31/2018

12:33 PM Issue #1269 (Resolved): Verilator supports assert but not assume
Perfect, thanks. Fixed in git towards 3.919.
Wilson Snyder
04:26 AM Issue #1269: Verilator supports assert but not assume
Ok, sure and (hopefully) done. Please consider the attached (updated) patch,
Dan
Dan Gisselquist
02:48 AM Issue #1269 (Confirmed): Verilator supports assert but not assume
Good point. The catch is if a user misuses the statement they might get errors like "Unexpected assert" instead of "... Wilson Snyder
01:37 AM Issue #1269: Verilator supports assert but not assume
That patch didn't come through properly. Here it is in code, and as an attached file.... Dan Gisselquist
01:35 AM Issue #1269 (Closed): Verilator supports assert but not assume
According to the 2004 Accellera specification, section 17.13.2 regarding the assume statement,
> For simulation, t...
Dan Gisselquist

01/30/2018

12:08 AM Issue #1268 (Resolved): tracing_x examples do not generate proper waveform with verilator 3.918
Yup, got botched when recently revamped examples, sorry about that.
Fixed in git towards 3.919.
Wilson Snyder
 

Also available in: Atom